Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Hou Zhiqiang | a7294ab | 2016-12-13 14:54:16 +0800 | [diff] [blame] | 2 | /* |
Wasim Khan | c81b1ea | 2019-11-15 09:23:34 +0000 | [diff] [blame] | 3 | * Copyright 2017-2019 NXP |
Hou Zhiqiang | a7294ab | 2016-12-13 14:54:16 +0800 | [diff] [blame] | 4 | * Copyright 2014-2015 Freescale Semiconductor, Inc. |
| 5 | * Layerscape PCIe driver |
Hou Zhiqiang | a7294ab | 2016-12-13 14:54:16 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef _PCIE_LAYERSCAPE_H_ |
| 9 | #define _PCIE_LAYERSCAPE_H_ |
| 10 | #include <pci.h> |
Minghuan Lian | 9fa2a4f | 2016-12-13 14:54:23 +0800 | [diff] [blame] | 11 | #include <dm.h> |
Hou Zhiqiang | a7294ab | 2016-12-13 14:54:16 +0800 | [diff] [blame] | 12 | |
| 13 | #ifndef CONFIG_SYS_PCI_MEMORY_BUS |
| 14 | #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE |
| 15 | #endif |
| 16 | |
| 17 | #ifndef CONFIG_SYS_PCI_MEMORY_PHYS |
| 18 | #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE |
| 19 | #endif |
| 20 | |
| 21 | #ifndef CONFIG_SYS_PCI_MEMORY_SIZE |
| 22 | #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ |
| 23 | #endif |
| 24 | |
| 25 | #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE |
| 26 | #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR |
| 27 | #endif |
| 28 | |
Hou Zhiqiang | 3d8553f | 2017-03-03 12:35:09 +0800 | [diff] [blame] | 29 | #define PCIE_PHYS_SIZE 0x200000000 |
| 30 | #define LS2088A_PCIE_PHYS_SIZE 0x800000000 |
| 31 | #define LS2088A_PCIE1_PHYS_ADDR 0x2000000000 |
| 32 | |
Hou Zhiqiang | a7294ab | 2016-12-13 14:54:16 +0800 | [diff] [blame] | 33 | /* iATU registers */ |
| 34 | #define PCIE_ATU_VIEWPORT 0x900 |
| 35 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
| 36 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
| 37 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
| 38 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
| 39 | #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) |
| 40 | #define PCIE_ATU_REGION_INDEX3 (0x3 << 0) |
| 41 | #define PCIE_ATU_REGION_NUM 6 |
| 42 | #define PCIE_ATU_CR1 0x904 |
| 43 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) |
| 44 | #define PCIE_ATU_TYPE_IO (0x2 << 0) |
| 45 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
| 46 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
| 47 | #define PCIE_ATU_CR2 0x908 |
| 48 | #define PCIE_ATU_ENABLE (0x1 << 31) |
| 49 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
| 50 | #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8) |
| 51 | #define PCIE_ATU_LOWER_BASE 0x90C |
| 52 | #define PCIE_ATU_UPPER_BASE 0x910 |
| 53 | #define PCIE_ATU_LIMIT 0x914 |
| 54 | #define PCIE_ATU_LOWER_TARGET 0x918 |
| 55 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
| 56 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
| 57 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
| 58 | #define PCIE_ATU_UPPER_TARGET 0x91C |
| 59 | |
| 60 | /* DBI registers */ |
| 61 | #define PCIE_SRIOV 0x178 |
| 62 | #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ |
| 63 | #define PCIE_DBI_RO_WR_EN 0x8bc |
| 64 | |
| 65 | #define PCIE_LINK_CAP 0x7c |
| 66 | #define PCIE_LINK_SPEED_MASK 0xf |
| 67 | #define PCIE_LINK_WIDTH_MASK 0x3f0 |
| 68 | #define PCIE_LINK_STA 0x82 |
| 69 | |
| 70 | #define LTSSM_STATE_MASK 0x3f |
| 71 | #define LTSSM_PCIE_L0 0x11 /* L0 state */ |
| 72 | |
| 73 | #define PCIE_DBI_SIZE 0x100000 /* 1M */ |
| 74 | |
| 75 | #define PCIE_LCTRL0_CFG2_ENABLE (1 << 31) |
| 76 | #define PCIE_LCTRL0_VF(vf) ((vf) << 22) |
| 77 | #define PCIE_LCTRL0_PF(pf) ((pf) << 16) |
| 78 | #define PCIE_LCTRL0_VF_ACTIVE (1 << 21) |
| 79 | #define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \ |
| 80 | PCIE_LCTRL0_VF(vf) | \ |
| 81 | ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \ |
| 82 | PCIE_LCTRL0_CFG2_ENABLE) |
| 83 | |
| 84 | #define PCIE_NO_SRIOV_BAR_BASE 0x1000 |
| 85 | |
| 86 | #define PCIE_PF_NUM 2 |
| 87 | #define PCIE_VF_NUM 64 |
| 88 | |
| 89 | #define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ |
| 90 | #define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ |
| 91 | #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ |
| 92 | #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ |
| 93 | |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 94 | /* LUT registers */ |
| 95 | #define PCIE_LUT_UDR(n) (0x800 + (n) * 8) |
| 96 | #define PCIE_LUT_LDR(n) (0x804 + (n) * 8) |
| 97 | #define PCIE_LUT_ENABLE (1 << 31) |
| 98 | #define PCIE_LUT_ENTRY_COUNT 32 |
| 99 | |
| 100 | /* PF Controll registers */ |
Hou Zhiqiang | d170aca | 2017-02-10 15:42:11 +0800 | [diff] [blame] | 101 | #define PCIE_PF_CONFIG 0x14 |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 102 | #define PCIE_PF_VF_CTRL 0x7F8 |
| 103 | #define PCIE_PF_DBG 0x7FC |
Hou Zhiqiang | d170aca | 2017-02-10 15:42:11 +0800 | [diff] [blame] | 104 | #define PCIE_CONFIG_READY (1 << 0) |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 105 | |
| 106 | #define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) |
| 107 | #define PCIE_SYS_BASE_ADDR 0x3400000 |
| 108 | #define PCIE_CCSR_SIZE 0x0100000 |
| 109 | |
| 110 | /* CS2 */ |
| 111 | #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ |
| 112 | |
| 113 | #define SVR_LS102XA 0 |
| 114 | #define SVR_VAR_PER_SHIFT 8 |
| 115 | #define SVR_LS102XA_MASK 0x700 |
Hou Zhiqiang | 3d8553f | 2017-03-03 12:35:09 +0800 | [diff] [blame] | 116 | #define SVR_LS2088A 0x870900 |
| 117 | #define SVR_LS2084A 0x870910 |
| 118 | #define SVR_LS2048A 0x870920 |
| 119 | #define SVR_LS2044A 0x870930 |
Santan Kumar | ec8a7d7 | 2017-06-09 11:48:08 +0530 | [diff] [blame] | 120 | #define SVR_LS2081A 0x870918 |
| 121 | #define SVR_LS2041A 0x870914 |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 122 | |
| 123 | /* LS1021a PCIE space */ |
| 124 | #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL |
| 125 | #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL |
| 126 | |
| 127 | /* LS1021a PEX1/2 Misc Ports Status Register */ |
| 128 | #define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) |
| 129 | #define LS1021_LTSSM_STATE_SHIFT 20 |
| 130 | |
| 131 | struct ls_pcie { |
| 132 | int idx; |
| 133 | struct list_head list; |
| 134 | struct udevice *bus; |
| 135 | struct fdt_resource dbi_res; |
| 136 | struct fdt_resource lut_res; |
| 137 | struct fdt_resource ctrl_res; |
| 138 | struct fdt_resource cfg_res; |
| 139 | void __iomem *dbi; |
| 140 | void __iomem *lut; |
| 141 | void __iomem *ctrl; |
| 142 | void __iomem *cfg0; |
| 143 | void __iomem *cfg1; |
| 144 | bool big_endian; |
| 145 | bool enabled; |
| 146 | int next_lut_index; |
Wasim Khan | c81b1ea | 2019-11-15 09:23:34 +0000 | [diff] [blame] | 147 | int stream_id_cur; |
Xiaowei Bao | 5bd3c9d | 2018-10-26 09:56:24 +0800 | [diff] [blame] | 148 | int mode; |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 149 | }; |
| 150 | |
| 151 | extern struct list_head ls_pcie_list; |
| 152 | |
Hou Zhiqiang | a7294ab | 2016-12-13 14:54:16 +0800 | [diff] [blame] | 153 | #endif /* _PCIE_LAYERSCAPE_H_ */ |