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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05302/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05305 */
6
York Sun0b665132013-10-22 12:39:02 -07007#ifndef __FSL_IFC_H
8#define __FSL_IFC_H
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05309
Mingkai Hu362ee042013-05-16 10:18:13 +080010#ifdef CONFIG_FSL_IFC
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053011#include <config.h>
12#include <common.h>
Simon Glass457e51c2017-05-17 08:23:10 -060013#ifdef CONFIG_ARM
14#include <asm/arch/soc.h>
15#endif
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053016
Prabhakar Kushwaha591dd192014-06-14 08:48:19 +053017#define FSL_IFC_V1_1_0 0x01010000
18#define FSL_IFC_V2_0_0 0x02000000
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053019
20#ifdef CONFIG_SYS_FSL_IFC_LE
21#define ifc_in32(a) in_le32(a)
22#define ifc_out32(a, v) out_le32(a, v)
23#define ifc_in16(a) in_le16(a)
Scott Woodd3963722015-06-26 19:03:26 -050024#define ifc_out16(a, v) out_le16(a, v)
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053025#elif defined(CONFIG_SYS_FSL_IFC_BE)
26#define ifc_in32(a) in_be32(a)
27#define ifc_out32(a, v) out_be32(a, v)
28#define ifc_in16(a) in_be16(a)
Scott Woodd3963722015-06-26 19:03:26 -050029#define ifc_out16(a, v) out_be16(a, v)
Prabhakar Kushwaha1b4175d2014-01-18 12:28:30 +053030#else
31#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
32#endif
33
34
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053035/*
36 * CSPR - Chip Select Property Register
37 */
38#define CSPR_BA 0xFFFF0000
39#define CSPR_BA_SHIFT 16
40#define CSPR_PORT_SIZE 0x00000180
41#define CSPR_PORT_SIZE_SHIFT 7
42/* Port Size 8 bit */
43#define CSPR_PORT_SIZE_8 0x00000080
44/* Port Size 16 bit */
45#define CSPR_PORT_SIZE_16 0x00000100
46/* Port Size 32 bit */
47#define CSPR_PORT_SIZE_32 0x00000180
48/* Write Protect */
49#define CSPR_WP 0x00000040
50#define CSPR_WP_SHIFT 6
51/* Machine Select */
52#define CSPR_MSEL 0x00000006
53#define CSPR_MSEL_SHIFT 1
54/* NOR */
55#define CSPR_MSEL_NOR 0x00000000
56/* NAND */
57#define CSPR_MSEL_NAND 0x00000002
58/* GPCM */
59#define CSPR_MSEL_GPCM 0x00000004
60/* Bank Valid */
61#define CSPR_V 0x00000001
62#define CSPR_V_SHIFT 0
63
64/* Convert an address into the right format for the CSPR Registers */
65#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
66
67/*
68 * Address Mask Register
69 */
70#define IFC_AMASK_MASK 0xFFFF0000
71#define IFC_AMASK_SHIFT 16
72#define IFC_AMASK(n) (IFC_AMASK_MASK << \
Rajesh Bhagat088d52c2018-11-05 18:01:19 +000073 (LOG2(n) - IFC_AMASK_SHIFT))
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053074
75/*
76 * Chip Select Option Register IFC_NAND Machine
77 */
78/* Enable ECC Encoder */
79#define CSOR_NAND_ECC_ENC_EN 0x80000000
Dipen Dudhat52f90da2011-03-22 09:27:39 +053080#define CSOR_NAND_ECC_MODE_MASK 0x30000000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +053081/* 4 bit correction per 520 Byte sector */
82#define CSOR_NAND_ECC_MODE_4 0x00000000
83/* 8 bit correction per 528 Byte sector */
84#define CSOR_NAND_ECC_MODE_8 0x10000000
85/* Enable ECC Decoder */
86#define CSOR_NAND_ECC_DEC_EN 0x04000000
87/* Row Address Length */
88#define CSOR_NAND_RAL_MASK 0x01800000
89#define CSOR_NAND_RAL_SHIFT 20
90#define CSOR_NAND_RAL_1 0x00000000
91#define CSOR_NAND_RAL_2 0x00800000
92#define CSOR_NAND_RAL_3 0x01000000
93#define CSOR_NAND_RAL_4 0x01800000
94/* Page Size 512b, 2k, 4k */
95#define CSOR_NAND_PGS_MASK 0x00180000
96#define CSOR_NAND_PGS_SHIFT 16
97#define CSOR_NAND_PGS_512 0x00000000
98#define CSOR_NAND_PGS_2K 0x00080000
99#define CSOR_NAND_PGS_4K 0x00100000
Prabhakar Kushwaha71220f82013-10-04 10:05:36 +0530100#define CSOR_NAND_PGS_8K 0x00180000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530101/* Spare region Size */
102#define CSOR_NAND_SPRZ_MASK 0x0000E000
103#define CSOR_NAND_SPRZ_SHIFT 13
104#define CSOR_NAND_SPRZ_16 0x00000000
105#define CSOR_NAND_SPRZ_64 0x00002000
106#define CSOR_NAND_SPRZ_128 0x00004000
107#define CSOR_NAND_SPRZ_210 0x00006000
108#define CSOR_NAND_SPRZ_218 0x00008000
109#define CSOR_NAND_SPRZ_224 0x0000A000
Prabhakar Kushwaha71220f82013-10-04 10:05:36 +0530110#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530111/* Pages Per Block */
112#define CSOR_NAND_PB_MASK 0x00000700
113#define CSOR_NAND_PB_SHIFT 8
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000114#define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530115/* Time for Read Enable High to Output High Impedance */
116#define CSOR_NAND_TRHZ_MASK 0x0000001C
117#define CSOR_NAND_TRHZ_SHIFT 2
118#define CSOR_NAND_TRHZ_20 0x00000000
119#define CSOR_NAND_TRHZ_40 0x00000004
120#define CSOR_NAND_TRHZ_60 0x00000008
121#define CSOR_NAND_TRHZ_80 0x0000000C
122#define CSOR_NAND_TRHZ_100 0x00000010
123/* Buffer control disable */
124#define CSOR_NAND_BCTLD 0x00000001
125
126/*
127 * Chip Select Option Register - NOR Flash Mode
128 */
129/* Enable Address shift Mode */
130#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
131/* Page Read Enable from NOR device */
132#define CSOR_NOR_PGRD_EN 0x10000000
133/* AVD Toggle Enable during Burst Program */
134#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
135/* Address Data Multiplexing Shift */
136#define CSOR_NOR_ADM_MASK 0x0003E000
137#define CSOR_NOR_ADM_SHIFT_SHIFT 13
138#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
139/* Type of the NOR device hooked */
140#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
141#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
142/* Time for Read Enable High to Output High Impedance */
143#define CSOR_NOR_TRHZ_MASK 0x0000001C
144#define CSOR_NOR_TRHZ_SHIFT 2
145#define CSOR_NOR_TRHZ_20 0x00000000
146#define CSOR_NOR_TRHZ_40 0x00000004
147#define CSOR_NOR_TRHZ_60 0x00000008
148#define CSOR_NOR_TRHZ_80 0x0000000C
149#define CSOR_NOR_TRHZ_100 0x00000010
150/* Buffer control disable */
151#define CSOR_NOR_BCTLD 0x00000001
152
153/*
154 * Chip Select Option Register - GPCM Mode
155 */
156/* GPCM Mode - Normal */
157#define CSOR_GPCM_GPMODE_NORMAL 0x00000000
158/* GPCM Mode - GenericASIC */
159#define CSOR_GPCM_GPMODE_ASIC 0x80000000
160/* Parity Mode odd/even */
161#define CSOR_GPCM_PARITY_EVEN 0x40000000
162/* Parity Checking enable/disable */
163#define CSOR_GPCM_PAR_EN 0x20000000
164/* GPCM Timeout Count */
165#define CSOR_GPCM_GPTO_MASK 0x0F000000
166#define CSOR_GPCM_GPTO_SHIFT 24
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000167#define CSOR_GPCM_GPTO(n) ((LOG2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530168/* GPCM External Access Termination mode for read access */
169#define CSOR_GPCM_RGETA_EXT 0x00080000
170/* GPCM External Access Termination mode for write access */
171#define CSOR_GPCM_WGETA_EXT 0x00040000
172/* Address Data Multiplexing Shift */
173#define CSOR_GPCM_ADM_MASK 0x0003E000
174#define CSOR_GPCM_ADM_SHIFT_SHIFT 13
175#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
176/* Generic ASIC Parity error indication delay */
177#define CSOR_GPCM_GAPERRD_MASK 0x00000180
178#define CSOR_GPCM_GAPERRD_SHIFT 7
179#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
180/* Time for Read Enable High to Output High Impedance */
181#define CSOR_GPCM_TRHZ_MASK 0x0000001C
182#define CSOR_GPCM_TRHZ_20 0x00000000
183#define CSOR_GPCM_TRHZ_40 0x00000004
184#define CSOR_GPCM_TRHZ_60 0x00000008
185#define CSOR_GPCM_TRHZ_80 0x0000000C
186#define CSOR_GPCM_TRHZ_100 0x00000010
187/* Buffer control disable */
188#define CSOR_GPCM_BCTLD 0x00000001
189
190/*
191 * Flash Timing Registers (FTIM0 - FTIM2_CSn)
192 */
193/*
194 * FTIM0 - NAND Flash Mode
195 */
196#define FTIM0_NAND 0x7EFF3F3F
197#define FTIM0_NAND_TCCST_SHIFT 25
198#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT)
199#define FTIM0_NAND_TWP_SHIFT 16
200#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT)
201#define FTIM0_NAND_TWCHT_SHIFT 8
202#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT)
203#define FTIM0_NAND_TWH_SHIFT 0
204#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT)
205/*
206 * FTIM1 - NAND Flash Mode
207 */
208#define FTIM1_NAND 0xFFFF3FFF
209#define FTIM1_NAND_TADLE_SHIFT 24
210#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT)
211#define FTIM1_NAND_TWBE_SHIFT 16
212#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT)
213#define FTIM1_NAND_TRR_SHIFT 8
214#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT)
215#define FTIM1_NAND_TRP_SHIFT 0
216#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT)
217/*
218 * FTIM2 - NAND Flash Mode
219 */
220#define FTIM2_NAND 0x1FE1F8FF
221#define FTIM2_NAND_TRAD_SHIFT 21
222#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT)
223#define FTIM2_NAND_TREH_SHIFT 11
224#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT)
225#define FTIM2_NAND_TWHRE_SHIFT 0
226#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT)
227/*
228 * FTIM3 - NAND Flash Mode
229 */
230#define FTIM3_NAND 0xFF000000
231#define FTIM3_NAND_TWW_SHIFT 24
232#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT)
233
234/*
235 * FTIM0 - NOR Flash Mode
236 */
237#define FTIM0_NOR 0xF03F3F3F
238#define FTIM0_NOR_TACSE_SHIFT 28
239#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
240#define FTIM0_NOR_TEADC_SHIFT 16
241#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
242#define FTIM0_NOR_TAVDS_SHIFT 8
243#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
244#define FTIM0_NOR_TEAHC_SHIFT 0
245#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
246/*
247 * FTIM1 - NOR Flash Mode
248 */
249#define FTIM1_NOR 0xFF003F3F
250#define FTIM1_NOR_TACO_SHIFT 24
251#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
252#define FTIM1_NOR_TRAD_NOR_SHIFT 8
253#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
254#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
255#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
256/*
257 * FTIM2 - NOR Flash Mode
258 */
259#define FTIM2_NOR 0x0F3CFCFF
260#define FTIM2_NOR_TCS_SHIFT 24
261#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
262#define FTIM2_NOR_TCH_SHIFT 18
263#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
264#define FTIM2_NOR_TWPH_SHIFT 10
265#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
266#define FTIM2_NOR_TWP_SHIFT 0
267#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
268
269/*
270 * FTIM0 - Normal GPCM Mode
271 */
272#define FTIM0_GPCM 0xF03F3F3F
273#define FTIM0_GPCM_TACSE_SHIFT 28
274#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
275#define FTIM0_GPCM_TEADC_SHIFT 16
276#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
277#define FTIM0_GPCM_TAVDS_SHIFT 8
278#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
279#define FTIM0_GPCM_TEAHC_SHIFT 0
280#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
281/*
282 * FTIM1 - Normal GPCM Mode
283 */
284#define FTIM1_GPCM 0xFF003F00
285#define FTIM1_GPCM_TACO_SHIFT 24
286#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
287#define FTIM1_GPCM_TRAD_SHIFT 8
288#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
289/*
290 * FTIM2 - Normal GPCM Mode
291 */
292#define FTIM2_GPCM 0x0F3C00FF
293#define FTIM2_GPCM_TCS_SHIFT 24
294#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
295#define FTIM2_GPCM_TCH_SHIFT 18
296#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
297#define FTIM2_GPCM_TWP_SHIFT 0
298#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
299
300/*
301 * Ready Busy Status Register (RB_STAT)
302 */
303/* CSn is READY */
304#define IFC_RB_STAT_READY_CS0 0x80000000
305#define IFC_RB_STAT_READY_CS1 0x40000000
306#define IFC_RB_STAT_READY_CS2 0x20000000
307#define IFC_RB_STAT_READY_CS3 0x10000000
308
309/*
310 * General Control Register (GCR)
311 */
312#define IFC_GCR_MASK 0x8000F800
313/* reset all IFC hardware */
314#define IFC_GCR_SOFT_RST_ALL 0x80000000
315/* Turnaroud Time of external buffer */
316#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
317#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
318
319/*
320 * Common Event and Error Status Register (CM_EVTER_STAT)
321 */
322/* Chip select error */
323#define IFC_CM_EVTER_STAT_CSER 0x80000000
324
325/*
326 * Common Event and Error Enable Register (CM_EVTER_EN)
327 */
328/* Chip select error checking enable */
329#define IFC_CM_EVTER_EN_CSEREN 0x80000000
330
331/*
332 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
333 */
334/* Chip select error interrupt enable */
335#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
336
337/*
338 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
339 */
340/* transaction type of error Read/Write */
341#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
342#define IFC_CM_ERATTR0_ERAID 0x0FF00000
343#define IFC_CM_ERATTR0_ESRCID 0x0000FF00
344
345/*
346 * Clock Control Register (CCR)
347 */
348#define IFC_CCR_MASK 0x0F0F8800
349/* Clock division ratio */
350#define IFC_CCR_CLK_DIV_MASK 0x0F000000
351#define IFC_CCR_CLK_DIV_SHIFT 24
352#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
353/* IFC Clock Delay */
354#define IFC_CCR_CLK_DLY_MASK 0x000F0000
355#define IFC_CCR_CLK_DLY_SHIFT 16
356#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
357/* Invert IFC clock before sending out */
358#define IFC_CCR_INV_CLK_EN 0x00008000
359/* Fedback IFC Clock */
360#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
361
362/*
363 * Clock Status Register (CSR)
364 */
365/* Clk is stable */
366#define IFC_CSR_CLK_STAT_STABLE 0x80000000
367
368/*
369 * IFC_NAND Machine Specific Registers
370 */
371/*
372 * NAND Configuration Register (NCFGR)
373 */
374/* Auto Boot Mode */
375#define IFC_NAND_NCFGR_BOOT 0x80000000
Prabhakar Kushwaha04818bb2014-06-12 12:14:00 +0530376/* SRAM INIT EN */
377#define IFC_NAND_SRAM_INIT_EN 0x20000000
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530378/* Addressing Mode-ROW0+n/COL0 */
379#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
380/* Addressing Mode-ROW0+n/COL0+n */
381#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
382/* Number of loop iterations of FIR sequences for multi page operations */
383#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
384#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
385#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
386/* Number of wait cycles */
387#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
388#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
389
390/*
391 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
392 */
393/* General purpose FCM flash command bytes CMD0-CMD7 */
394#define IFC_NAND_FCR0_CMD0 0xFF000000
395#define IFC_NAND_FCR0_CMD0_SHIFT 24
396#define IFC_NAND_FCR0_CMD1 0x00FF0000
397#define IFC_NAND_FCR0_CMD1_SHIFT 16
398#define IFC_NAND_FCR0_CMD2 0x0000FF00
399#define IFC_NAND_FCR0_CMD2_SHIFT 8
400#define IFC_NAND_FCR0_CMD3 0x000000FF
401#define IFC_NAND_FCR0_CMD3_SHIFT 0
402#define IFC_NAND_FCR1_CMD4 0xFF000000
403#define IFC_NAND_FCR1_CMD4_SHIFT 24
404#define IFC_NAND_FCR1_CMD5 0x00FF0000
405#define IFC_NAND_FCR1_CMD5_SHIFT 16
406#define IFC_NAND_FCR1_CMD6 0x0000FF00
407#define IFC_NAND_FCR1_CMD6_SHIFT 8
408#define IFC_NAND_FCR1_CMD7 0x000000FF
409#define IFC_NAND_FCR1_CMD7_SHIFT 0
410
411/*
412 * Flash ROW and COL Address Register (ROWn, COLn)
413 */
414/* Main/spare region locator */
415#define IFC_NAND_COL_MS 0x80000000
416/* Column Address */
417#define IFC_NAND_COL_CA_MASK 0x00000FFF
418
419/*
420 * NAND Flash Byte Count Register (NAND_BC)
421 */
422/* Byte Count for read/Write */
423#define IFC_NAND_BC 0x000001FF
424
425/*
426 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
427 */
428/* NAND Machine specific opcodes OP0-OP14*/
429#define IFC_NAND_FIR0_OP0 0xFC000000
430#define IFC_NAND_FIR0_OP0_SHIFT 26
431#define IFC_NAND_FIR0_OP1 0x03F00000
432#define IFC_NAND_FIR0_OP1_SHIFT 20
433#define IFC_NAND_FIR0_OP2 0x000FC000
434#define IFC_NAND_FIR0_OP2_SHIFT 14
435#define IFC_NAND_FIR0_OP3 0x00003F00
436#define IFC_NAND_FIR0_OP3_SHIFT 8
437#define IFC_NAND_FIR0_OP4 0x000000FC
438#define IFC_NAND_FIR0_OP4_SHIFT 2
439#define IFC_NAND_FIR1_OP5 0xFC000000
440#define IFC_NAND_FIR1_OP5_SHIFT 26
441#define IFC_NAND_FIR1_OP6 0x03F00000
442#define IFC_NAND_FIR1_OP6_SHIFT 20
443#define IFC_NAND_FIR1_OP7 0x000FC000
444#define IFC_NAND_FIR1_OP7_SHIFT 14
445#define IFC_NAND_FIR1_OP8 0x00003F00
446#define IFC_NAND_FIR1_OP8_SHIFT 8
447#define IFC_NAND_FIR1_OP9 0x000000FC
448#define IFC_NAND_FIR1_OP9_SHIFT 2
449#define IFC_NAND_FIR2_OP10 0xFC000000
450#define IFC_NAND_FIR2_OP10_SHIFT 26
451#define IFC_NAND_FIR2_OP11 0x03F00000
452#define IFC_NAND_FIR2_OP11_SHIFT 20
453#define IFC_NAND_FIR2_OP12 0x000FC000
454#define IFC_NAND_FIR2_OP12_SHIFT 14
455#define IFC_NAND_FIR2_OP13 0x00003F00
456#define IFC_NAND_FIR2_OP13_SHIFT 8
457#define IFC_NAND_FIR2_OP14 0x000000FC
458#define IFC_NAND_FIR2_OP14_SHIFT 2
459
460/*
461 * Instruction opcodes to be programmed
462 * in FIR registers- 6bits
463 */
464enum ifc_nand_fir_opcodes {
465 IFC_FIR_OP_NOP,
466 IFC_FIR_OP_CA0,
467 IFC_FIR_OP_CA1,
468 IFC_FIR_OP_CA2,
469 IFC_FIR_OP_CA3,
470 IFC_FIR_OP_RA0,
471 IFC_FIR_OP_RA1,
472 IFC_FIR_OP_RA2,
473 IFC_FIR_OP_RA3,
474 IFC_FIR_OP_CMD0,
475 IFC_FIR_OP_CMD1,
476 IFC_FIR_OP_CMD2,
477 IFC_FIR_OP_CMD3,
478 IFC_FIR_OP_CMD4,
479 IFC_FIR_OP_CMD5,
480 IFC_FIR_OP_CMD6,
481 IFC_FIR_OP_CMD7,
482 IFC_FIR_OP_CW0,
483 IFC_FIR_OP_CW1,
484 IFC_FIR_OP_CW2,
485 IFC_FIR_OP_CW3,
486 IFC_FIR_OP_CW4,
487 IFC_FIR_OP_CW5,
488 IFC_FIR_OP_CW6,
489 IFC_FIR_OP_CW7,
490 IFC_FIR_OP_WBCD,
491 IFC_FIR_OP_RBCD,
492 IFC_FIR_OP_BTRD,
493 IFC_FIR_OP_RDSTAT,
494 IFC_FIR_OP_NWAIT,
495 IFC_FIR_OP_WFR,
496 IFC_FIR_OP_SBRD,
497 IFC_FIR_OP_UA,
498 IFC_FIR_OP_RB,
499};
500
501/*
502 * NAND Chip Select Register (NAND_CSEL)
503 */
504#define IFC_NAND_CSEL 0x0C000000
505#define IFC_NAND_CSEL_SHIFT 26
506#define IFC_NAND_CSEL_CS0 0x00000000
507#define IFC_NAND_CSEL_CS1 0x04000000
508#define IFC_NAND_CSEL_CS2 0x08000000
509#define IFC_NAND_CSEL_CS3 0x0C000000
510
511/*
512 * NAND Operation Sequence Start (NANDSEQ_STRT)
513 */
514/* NAND Flash Operation Start */
515#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
516/* Automatic Erase */
517#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
518/* Automatic Program */
519#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
520/* Automatic Copyback */
521#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
522/* Automatic Read Operation */
523#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
524/* Automatic Status Read */
525#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
526
527/*
528 * NAND Event and Error Status Register (NAND_EVTER_STAT)
529 */
530/* Operation Complete */
531#define IFC_NAND_EVTER_STAT_OPC 0x80000000
532/* Flash Timeout Error */
533#define IFC_NAND_EVTER_STAT_FTOER 0x08000000
534/* Write Protect Error */
535#define IFC_NAND_EVTER_STAT_WPER 0x04000000
536/* ECC Error */
537#define IFC_NAND_EVTER_STAT_ECCER 0x02000000
538/* RCW Load Done */
539#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
540/* Boot Loadr Done */
541#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
542/* Bad Block Indicator search select */
543#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
544
545/*
546 * NAND Flash Page Read Completion Event Status Register
547 * (PGRDCMPL_EVT_STAT)
548 */
549#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
550/* Small Page 0-15 Done */
551#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
552/* Large Page(2K) 0-3 Done */
553#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
554/* Large Page(4K) 0-1 Done */
555#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
556
557/*
558 * NAND Event and Error Enable Register (NAND_EVTER_EN)
559 */
560/* Operation complete event enable */
561#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
562/* Page read complete event enable */
563#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
564/* Flash Timeout error enable */
565#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
566/* Write Protect error enable */
567#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
568/* ECC error logging enable */
569#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
570
571/*
572 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
573 */
574/* Enable interrupt for operation complete */
575#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
576/* Enable interrupt for Page read complete */
577#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
578/* Enable interrupt for Flash timeout error */
579#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
580/* Enable interrupt for Write protect error */
581#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
582/* Enable interrupt for ECC error*/
583#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
584
585/*
586 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
587 */
588#define IFC_NAND_ERATTR0_MASK 0x0C080000
589/* Error on CS0-3 for NAND */
590#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
591#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
592#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
593#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
594/* Transaction type of error Read/Write */
595#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
596
597/*
598 * NAND Flash Status Register (NAND_FSR)
599 */
600/* First byte of data read from read status op */
601#define IFC_NAND_NFSR_RS0 0xFF000000
602/* Second byte of data read from read status op */
603#define IFC_NAND_NFSR_RS1 0x00FF0000
604
605/*
606 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
607 */
608/* Number of ECC errors on sector n (n = 0-15) */
609#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
610#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
611#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
612#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
613#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
614#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
615#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
616#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
617#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
618#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
619#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
620#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
621#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
622#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
623#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
624#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
625#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
626#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
627#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
628#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
629#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
630#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
631#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
632#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
633#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
634#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
635#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
636#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
637#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
638#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
639#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
640#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
641
642/*
643 * NAND Control Register (NANDCR)
644 */
645#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
646#define IFC_NAND_NCR_FTOCNT_SHIFT 25
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000647#define IFC_NAND_NCR_FTOCNT(n) ((LOG2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530648
649/*
650 * NAND_AUTOBOOT_TRGR
651 */
652/* Trigger RCW load */
653#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
654/* Trigget Auto Boot */
655#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
656
657/*
658 * NAND_MDR
659 */
660/* 1st read data byte when opcode SBRD */
661#define IFC_NAND_MDR_RDATA0 0xFF000000
662/* 2nd read data byte when opcode SBRD */
663#define IFC_NAND_MDR_RDATA1 0x00FF0000
664
665/*
666 * NOR Machine Specific Registers
667 */
668/*
669 * NOR Event and Error Status Register (NOR_EVTER_STAT)
670 */
671/* NOR Command Sequence Operation Complete */
672#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
673/* Write Protect Error */
674#define IFC_NOR_EVTER_STAT_WPER 0x04000000
675/* Command Sequence Timeout Error */
676#define IFC_NOR_EVTER_STAT_STOER 0x01000000
677
678/*
679 * NOR Event and Error Enable Register (NOR_EVTER_EN)
680 */
681/* NOR Command Seq complete event enable */
682#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
683/* Write Protect Error Checking Enable */
684#define IFC_NOR_EVTER_EN_WPEREN 0x04000000
685/* Timeout Error Enable */
686#define IFC_NOR_EVTER_EN_STOEREN 0x01000000
687
688/*
689 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
690 */
691/* Enable interrupt for OPC complete */
692#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
693/* Enable interrupt for write protect error */
694#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
695/* Enable interrupt for timeout error */
696#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
697
698/*
699 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
700 */
701/* Source ID for error transaction */
702#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
703/* AXI ID for error transation */
704#define IFC_NOR_ERATTR0_ERAID 0x000FF000
705/* Chip select corresponds to NOR error */
706#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
707#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
708#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
709#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
710/* Type of transaction read/write */
711#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
712
713/*
714 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
715 */
716#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
717#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
718
719/*
720 * NOR Control Register (NORCR)
721 */
722#define IFC_NORCR_MASK 0x0F0F0000
723/* No. of Address/Data Phase */
724#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
725#define IFC_NORCR_NUM_PHASE_SHIFT 24
726#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
727/* Sequence Timeout Count */
728#define IFC_NORCR_STOCNT_MASK 0x000F0000
729#define IFC_NORCR_STOCNT_SHIFT 16
Rajesh Bhagat088d52c2018-11-05 18:01:19 +0000730#define IFC_NORCR_STOCNT(n) ((LOG2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530731
732/*
733 * GPCM Machine specific registers
734 */
735/*
736 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
737 */
738/* Timeout error */
739#define IFC_GPCM_EVTER_STAT_TOER 0x04000000
740/* Parity error */
741#define IFC_GPCM_EVTER_STAT_PER 0x01000000
742
743/*
744 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
745 */
746/* Timeout error enable */
747#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
748/* Parity error enable */
749#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
750
751/*
752 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
753 */
754/* Enable Interrupt for timeout error */
755#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
756/* Enable Interrupt for Parity error */
757#define IFC_GPCM_EEIER_PERIR_EN 0x01000000
758
759/*
760 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
761 */
762/* Source ID for error transaction */
763#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
764/* AXI ID for error transaction */
765#define IFC_GPCM_ERATTR0_ERAID 0x000FF000
766/* Chip select corresponds to GPCM error */
767#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
768#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
769#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
770#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
771/* Type of transaction read/Write */
772#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
773
774/*
775 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
776 */
777/* On which beat of address/data parity error is observed */
778#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
779/* Parity Error on byte */
780#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
781/* Parity Error reported in addr or data phase */
782#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
783
784/*
785 * GPCM Status Register (GPCM_STAT)
786 */
787#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
788
789
790#ifndef __ASSEMBLY__
791#include <asm/io.h>
792
793extern void print_ifc_regs(void);
794extern void init_early_memctl_regs(void);
York Sune77224e2014-03-19 13:52:34 -0700795void init_final_memctl_regs(void);
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530796
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700797#define IFC_RREGS_4KOFFSET (4*1024)
798#define IFC_RREGS_64KOFFSET (64*1024)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530799
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700800#define IFC_FCM_BASE_ADDR \
801 ((struct fsl_ifc_fcm *)CONFIG_SYS_IFC_ADDR)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530802
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700803#define get_ifc_cspr_ext(i) \
804 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext))
805#define get_ifc_cspr(i) \
806 (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr))
807#define get_ifc_csor_ext(i) \
808 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext))
809#define get_ifc_csor(i) \
810 (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor))
811#define get_ifc_amask(i) \
812 (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask))
813#define get_ifc_ftim(i, j) \
814 (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]))
815#define set_ifc_cspr_ext(i, v) \
816 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
817#define set_ifc_cspr(i, v) \
818 (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v))
819#define set_ifc_csor_ext(i, v) \
820 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v))
821#define set_ifc_csor(i, v) \
822 (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v))
823#define set_ifc_amask(i, v) \
824 (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v))
825#define set_ifc_ftim(i, j, v) \
826 (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v))
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530827
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530828enum ifc_chip_sel {
829 IFC_CS0,
830 IFC_CS1,
831 IFC_CS2,
832 IFC_CS3,
Mingkai Hu362ee042013-05-16 10:18:13 +0800833 IFC_CS4,
834 IFC_CS5,
835 IFC_CS6,
836 IFC_CS7,
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530837};
838
839enum ifc_ftims {
840 IFC_FTIM0,
841 IFC_FTIM1,
842 IFC_FTIM2,
843 IFC_FTIM3,
844};
845
846/*
847 * IFC Controller NAND Machine registers
848 */
849struct fsl_ifc_nand {
850 u32 ncfgr;
851 u32 res1[0x4];
852 u32 nand_fcr0;
853 u32 nand_fcr1;
854 u32 res2[0x8];
855 u32 row0;
856 u32 res3;
857 u32 col0;
858 u32 res4;
859 u32 row1;
860 u32 res5;
861 u32 col1;
862 u32 res6;
863 u32 row2;
864 u32 res7;
865 u32 col2;
866 u32 res8;
867 u32 row3;
868 u32 res9;
869 u32 col3;
870 u32 res10[0x24];
871 u32 nand_fbcr;
872 u32 res11;
873 u32 nand_fir0;
874 u32 nand_fir1;
875 u32 nand_fir2;
876 u32 res12[0x10];
877 u32 nand_csel;
878 u32 res13;
879 u32 nandseq_strt;
880 u32 res14;
881 u32 nand_evter_stat;
882 u32 res15;
883 u32 pgrdcmpl_evt_stat;
884 u32 res16[0x2];
885 u32 nand_evter_en;
886 u32 res17[0x2];
887 u32 nand_evter_intr_en;
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700888 u32 nand_vol_addr_stat;
889 u32 res18;
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530890 u32 nand_erattr0;
891 u32 nand_erattr1;
892 u32 res19[0x10];
893 u32 nand_fsr;
Jagdish Gediyaf195fad2018-03-24 02:55:51 +0530894 u32 res20[0x1];
895 u32 nand_eccstat[8];
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700896 u32 res21[0x1c];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530897 u32 nanndcr;
898 u32 res22[0x2];
899 u32 nand_autoboot_trgr;
900 u32 res23;
901 u32 nand_mdr;
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700902 u32 res24[0x1c];
903 u32 nand_dll_lowcfg0;
904 u32 nand_dll_lowcfg1;
905 u32 res25;
906 u32 nand_dll_lowstat;
907 u32 res26[0x3C];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530908};
909
910/*
911 * IFC controller NOR Machine registers
912 */
913struct fsl_ifc_nor {
914 u32 nor_evter_stat;
915 u32 res1[0x2];
916 u32 nor_evter_en;
917 u32 res2[0x2];
918 u32 nor_evter_intr_en;
919 u32 res3[0x2];
920 u32 nor_erattr0;
921 u32 nor_erattr1;
922 u32 nor_erattr2;
923 u32 res4[0x4];
924 u32 norcr;
925 u32 res5[0xEF];
926};
927
928/*
929 * IFC controller GPCM Machine registers
930 */
931struct fsl_ifc_gpcm {
932 u32 gpcm_evter_stat;
933 u32 res1[0x2];
934 u32 gpcm_evter_en;
935 u32 res2[0x2];
936 u32 gpcm_evter_intr_en;
937 u32 res3[0x2];
938 u32 gpcm_erattr0;
939 u32 gpcm_erattr1;
940 u32 gpcm_erattr2;
941 u32 gpcm_stat;
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530942};
943
Mingkai Hu362ee042013-05-16 10:18:13 +0800944#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
945#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
946#define IFC_CSPR_REG_LEN 148
947#define IFC_AMASK_REG_LEN 144
948#define IFC_CSOR_REG_LEN 144
949#define IFC_FTIM_REG_LEN 576
950
951#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \
952 CONFIG_SYS_FSL_IFC_BANK_COUNT
953#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \
954 CONFIG_SYS_FSL_IFC_BANK_COUNT
955#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \
956 CONFIG_SYS_FSL_IFC_BANK_COUNT
957#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \
958 CONFIG_SYS_FSL_IFC_BANK_COUNT
959#else
960#error IFC BANK count not vaild
961#endif
962#else
963#error IFC BANK count not defined
964#endif
965
966struct fsl_ifc_cspr {
967 u32 cspr_ext;
968 u32 cspr;
969 u32 res;
970};
971
972struct fsl_ifc_amask {
973 u32 amask;
974 u32 res[0x2];
975};
976
977struct fsl_ifc_csor {
978 u32 csor;
979 u32 csor_ext;
980 u32 res;
981};
982
983struct fsl_ifc_ftim {
984 u32 ftim[4];
985 u32 res[0x8];
986};
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530987
988/*
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700989 * IFC Controller Global Registers
990 * FCM - Flash control machine
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530991 */
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -0700992
993struct fsl_ifc_fcm {
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530994 u32 ifc_rev;
Kumar Galaffdf8892012-08-17 08:20:25 +0000995 u32 res1[0x2];
Mingkai Hu362ee042013-05-16 10:18:13 +0800996 struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
997 u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
998 struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
999 u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
1000 struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1001 u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
1002 struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
1003 u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301004 u32 rb_stat;
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -07001005 u32 rb_map;
1006 u32 wp_map;
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301007 u32 ifc_gcr;
Mingkai Hu362ee042013-05-16 10:18:13 +08001008 u32 res7[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301009 u32 cm_evter_stat;
Mingkai Hu362ee042013-05-16 10:18:13 +08001010 u32 res8[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301011 u32 cm_evter_en;
Mingkai Hu362ee042013-05-16 10:18:13 +08001012 u32 res9[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301013 u32 cm_evter_intr_en;
Mingkai Hu362ee042013-05-16 10:18:13 +08001014 u32 res10[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301015 u32 cm_erattr0;
1016 u32 cm_erattr1;
Mingkai Hu362ee042013-05-16 10:18:13 +08001017 u32 res11[0x2];
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301018 u32 ifc_ccr;
1019 u32 ifc_csr;
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -07001020 u32 ddr_ccr_low;
1021};
1022
1023struct fsl_ifc_runtime {
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301024 struct fsl_ifc_nand ifc_nand;
1025 struct fsl_ifc_nor ifc_nor;
1026 struct fsl_ifc_gpcm ifc_gpcm;
1027};
1028
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -07001029struct fsl_ifc {
1030 struct fsl_ifc_fcm *gregs;
1031 struct fsl_ifc_runtime *rregs;
1032};
1033
Pankit Garg9bd5fe72018-11-05 18:01:33 +00001034struct ifc_regs {
1035 const char *name;
1036 u32 pr;
1037 u32 pr_ext;
1038 u32 amask;
1039 u32 or;
1040 u32 ftim[4];
1041 u32 or_ext;
1042 u32 pr_final;
1043 u32 amask_final;
1044};
1045
1046struct ifc_regs_info {
1047 struct ifc_regs *regs;
1048 u32 cs_size;
1049};
1050
Poonam Aggrwal42aee642011-06-30 03:00:28 -05001051#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
1052#undef CSPR_MSEL_NOR
1053#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
1054#endif
Mingkai Hu362ee042013-05-16 10:18:13 +08001055#endif /* CONFIG_FSL_IFC */
Poonam Aggrwal42aee642011-06-30 03:00:28 -05001056
Dipen Dudhatd789b5f2011-01-20 16:29:35 +05301057#endif /* __ASSEMBLY__ */
York Sun0b665132013-10-22 12:39:02 -07001058#endif /* __FSL_IFC_H */