blob: 20baaf61307aa3f6a65165a5f17e7f36915634fc [file] [log] [blame]
Rick Chena1f24872019-04-02 15:56:40 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2019, Rick Chen <rick@andestech.com>
Sean Andersone86463f2020-09-28 10:52:24 -04004 * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
Rick Chena1f24872019-04-02 15:56:40 +08005 *
6 * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
7 * The PLMT block holds memory-mapped mtime register
8 * associated with timer tick.
9 */
10
Rick Chena1f24872019-04-02 15:56:40 +080011#include <dm.h>
Sean Andersone86463f2020-09-28 10:52:24 -040012#include <timer.h>
Rick Chena1f24872019-04-02 15:56:40 +080013#include <asm/io.h>
Simon Glass0fd3d912020-12-22 19:30:28 -070014#include <dm/device-internal.h>
Simon Glass61b29b82020-02-03 07:36:15 -070015#include <linux/err.h>
Rick Chena1f24872019-04-02 15:56:40 +080016
17/* mtime register */
18#define MTIME_REG(base) ((ulong)(base))
19
Pragnesh Patelbc8d12b2021-01-17 18:11:25 +053020static u64 notrace andes_plmt_get_count(struct udevice *dev)
Rick Chena1f24872019-04-02 15:56:40 +080021{
Simon Glass0fd3d912020-12-22 19:30:28 -070022 return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
Rick Chena1f24872019-04-02 15:56:40 +080023}
24
Pragnesh Patelbc8d12b2021-01-17 18:11:25 +053025#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
26/**
27 * timer_early_get_rate() - Get the timer rate before driver model
28 */
29unsigned long notrace timer_early_get_rate(void)
30{
31 return RISCV_MMODE_TIMER_FREQ;
32}
33
34/**
35 * timer_early_get_count() - Get the timer count before driver model
36 *
37 */
38u64 notrace timer_early_get_count(void)
39{
40 return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
41}
42#endif
43
Sean Andersone86463f2020-09-28 10:52:24 -040044static const struct timer_ops andes_plmt_ops = {
45 .get_count = andes_plmt_get_count,
46};
47
48static int andes_plmt_probe(struct udevice *dev)
49{
Simon Glass0fd3d912020-12-22 19:30:28 -070050 dev_set_priv(dev, dev_read_addr_ptr(dev));
51 if (!dev_get_priv(dev))
Sean Andersone86463f2020-09-28 10:52:24 -040052 return -EINVAL;
53
54 return timer_timebase_fallback(dev);
55}
56
Rick Chena1f24872019-04-02 15:56:40 +080057static const struct udevice_id andes_plmt_ids[] = {
Yu Chien Peter Lina5dfa3b2022-10-25 23:03:50 +080058 { .compatible = "andestech,plmt0" },
Rick Chena1f24872019-04-02 15:56:40 +080059 { }
60};
61
62U_BOOT_DRIVER(andes_plmt) = {
63 .name = "andes_plmt",
Sean Andersone86463f2020-09-28 10:52:24 -040064 .id = UCLASS_TIMER,
Rick Chena1f24872019-04-02 15:56:40 +080065 .of_match = andes_plmt_ids,
Sean Andersone86463f2020-09-28 10:52:24 -040066 .ops = &andes_plmt_ops,
67 .probe = andes_plmt_probe,
Rick Chena1f24872019-04-02 15:56:40 +080068 .flags = DM_FLAG_PRE_RELOC,
69};