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wdenk983fda82004-10-28 00:09:35 +00001/*
2 * MPC8220 Internal Memory Map
3 * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 *
5 * The Internal Memory Map of the 8220.
6 *
7 */
8#ifndef __IMMAP_MPC8220__
9#define __IMMAP_MPC8220__
10
11/*
12 * System configuration registers.
13 */
14typedef struct sys_conf {
15 u16 mbar; /* 0x00 */
16 u16 res1;
17
18 u16 res2; /* 0x04 */
19 u16 sdramds;
20
21 u32 res3[6]; /* 0x08 */
22
23 u32 cscfg[6]; /* 0x20 */
24
25 u32 res4[2]; /* 0x38 */
26
27 u8 res5[3]; /* 0x40 */
28 u8 rstctrl;
29
30 u8 res6[3]; /* 0x44 */
31 u8 rststat;
32
33 u32 res7[2]; /* 0x48 */
34
35 u32 jtagid; /* 0x50 */
36} sysconf8220_t;
37
38
39/*
40 * Memory controller registers.
41 */
42typedef struct mem_ctlr {
43 ushort mode; /* 0x100 */
44 ushort res1;
45 u32 ctrl; /* 0x104 */
46 u32 cfg1; /* 0x108 */
47 u32 cfg2; /* 0x10c */
48} memctl8220_t;
49
50/*
51 * XLB Arbitration registers
52 */
53typedef struct xlb_arb
54{
55 uint res1[16]; /* 0x200 */
56 uint config; /* 0x240 */
57 uint version; /* 0x244 */
58 uint status; /* 0x248 */
59 uint intEnable; /* 0x24c */
60 uint addrCap; /* 0x250 */
61 uint busSigCap; /* 0x254 */
62 uint addrTenTimeOut; /* 0x258 */
63 uint dataTenTimeOut; /* 0x25c */
64 uint busActTimeOut; /* 0x260 */
65 uint mastPriEn; /* 0x264 */
66 uint mastPriority; /* 0x268 */
67 uint baseAddr; /* 0x26c */
68} xlbarb8220_t;
69
70/*
71 * Flexbus registers
72 */
73typedef struct flexbus
74{
75 ushort csar0; /* 0x00 */
76 ushort res1;
77 uint csmr0; /* 0x04 */
78 uint cscr0; /* 0x08 */
79
80 ushort csar1; /* 0x0c */
81 ushort res2;
82 uint csmr1; /* 0x10 */
83 uint cscr1; /* 0x14 */
84
85 ushort csar2; /* 0x18 */
86 ushort res3;
87 uint csmr2; /* 0x1c */
88 uint cscr2; /* 0x20 */
89
90 ushort csar3; /* 0x24 */
91 ushort res4;
92 uint csmr3; /* 0x28 */
93 uint cscr3; /* 0x2c */
94
95 ushort csar4; /* 0x30 */
96 ushort res5;
97 uint csmr4; /* 0x34 */
98 uint cscr4; /* 0x38 */
99
100 ushort csar5; /* 0x3c */
101 ushort res6;
102 uint csmr5; /* 0x40 */
103 uint cscr5; /* 0x44 */
104} flexbus8220_t;
105
106/*
107 * GPIO registers
108 */
109typedef struct gpio
110{
111 u32 out; /* 0x00 */
112 u32 obs; /* 0x04 */
113 u32 obc; /* 0x08 */
114 u32 obt; /* 0x0c */
115 u32 en; /* 0x10 */
116 u32 ebs; /* 0x14 */
117 u32 ebc; /* 0x18 */
118 u32 ebt; /* 0x1c */
119 u32 mc; /* 0x20 */
120 u32 st; /* 0x24 */
121 u32 intr; /* 0x28 */
122} gpio8220_t;
123
124/*
125 * General Purpose Timer registers
126 */
127typedef struct gptimer
128{
129 u8 OCPW;
130 u8 OctIct;
131 u8 Control;
132 u8 Mode;
133
134 u16 Prescl; /* Prescale */
135 u16 Count; /* Count */
136
137 u16 PwmWid; /* PWM Width */
138 u8 PwmOp; /* Output Polarity */
139 u8 PwmLd; /* Immediate Update */
140
141 u16 Capture; /* Capture internal counter */
142 u8 OvfPin; /* Ovf and Pin */
143 u8 Int; /* Interrupts */
144} gptmr8220_t;
145
146/*
147 * PSC registers
148 */
149typedef struct psc
150{
151 u32 mr1_2; /* 0x00 Mode reg 1 & 2 */
152 u32 sr_csr; /* 0x04 Status/Clock Select reg */
153 u32 cr; /* 0x08 Command reg */
154 u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */
155 u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */
156 u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */
157 u32 ctur; /* 0x18 Counter Timer Upper reg */
158 u32 ctlr; /* 0x1c Counter Timer Lower reg */
159 u32 rsvd1[4]; /* 0x20 ... 0x2c */
160 u32 ivr; /* 0x30 Interrupt Vector reg */
161 u32 ipr; /* 0x34 Input Port reg */
162 u32 opsetr; /* 0x38 Output Port Set reg */
163 u32 opresetr; /* 0x3c Output Port Reset reg */
164 u32 sicr; /* 0x40 PSC/IrDA control reg */
165 u32 ircr1; /* 0x44 IrDA control reg 1*/
166 u32 ircr2; /* 0x48 IrDA control reg 2*/
167 u32 irsdr; /* 0x4c IrDA SIR Divide reg */
168 u32 irmdr; /* 0x50 IrDA MIR Divide reg */
169 u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */
170 u32 rfnum; /* 0x58 RX-FIFO counter */
171 u32 txnum; /* 0x5c TX-FIFO counter */
172 u32 rfdata; /* 0x60 RX-FIFO data */
173 u32 rfstat; /* 0x64 RX-FIFO status */
174 u32 rfcntl; /* 0x68 RX-FIFO control */
175 u32 rfalarm; /* 0x6c RX-FIFO alarm */
176 u32 rfrptr; /* 0x70 RX-FIFO read pointer */
177 u32 rfwptr; /* 0x74 RX-FIFO write pointer */
178 u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */
179 u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */
180
181 u32 tfdata; /* 0x80 TX-FIFO data */
182 u32 tfstat; /* 0x84 TX-FIFO status */
183 u32 tfcntl; /* 0x88 TX-FIFO control */
184 u32 tfalarm; /* 0x8c TX-FIFO alarm */
185 u32 tfrptr; /* 0x90 TX-FIFO read pointer */
186 u32 tfwptr; /* 0x94 TX-FIFO write pointer */
187 u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */
188 u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */
189} psc8220_t;
190
191/*
192 * Interrupt Controller registers
193 */
194typedef struct interrupt_controller {
195} intctl8220_t;
196
197
198/* Fast controllers
199*/
200
201/*
202 * I2C registers
203 */
204typedef struct i2c
205{
206 u8 adr; /* 0x00 */
207 u8 res1[3];
208 u8 fdr; /* 0x04 */
209 u8 res2[3];
210 u8 cr; /* 0x08 */
211 u8 res3[3];
212 u8 sr; /* 0x0C */
213 u8 res4[3];
214 u8 dr; /* 0x10 */
215 u8 res5[3];
216 u32 reserved0; /* 0x14 */
217 u32 reserved1; /* 0x18 */
218 u32 reserved2; /* 0x1c */
219 u8 icr; /* 0x20 */
220 u8 res6[3];
221} i2c8220_t;
222
223/*
224 * Port Configuration Registers
225 */
226typedef struct pcfg
227{
228 uint pcfg0; /* 0x00 */
229 uint pcfg1; /* 0x04 */
230 uint pcfg2; /* 0x08 */
231 uint pcfg3; /* 0x0c */
232} pcfg8220_t;
233
234/* ...and the whole thing wrapped up....
235*/
236typedef struct immap {
237 sysconf8220_t im_sysconf; /* System Configuration */
238 memctl8220_t im_memctl; /* Memory Controller */
239 xlbarb8220_t im_xlbarb; /* XLB Arbitration */
240 psc8220_t im_psc; /* PSC controller */
241 flexbus8220_t im_fb; /* FlexBus Controller */
242 i2c8220_t im_i2c; /* I2C control/status */
243 pcfg8220_t im_pcfg; /* Port configuration */
244} immap_t;
245
246#endif /* __IMMAP_MPC8220__ */