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Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
Stefan Roesef47b0482013-03-08 16:50:41 +01002 * (C) Copyright 2007-2013
Stefan Roeseb765ffb2007-06-15 08:18:01 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roeseb765ffb2007-06-15 08:18:01 +02006 */
7
8#include <common.h>
Stefan Roesec25dd8f2007-08-23 11:02:37 +02009#include <command.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020010#include <asm/ppc440.h>
Stefan Roese04e6c382007-07-04 10:06:30 +020011#include <asm/processor.h>
Stefan Roese09887762010-09-16 14:30:37 +020012#include <asm/ppc4xx-gpio.h>
Stefan Roese04e6c382007-07-04 10:06:30 +020013#include <asm/io.h>
Sascha Lauef14ae412010-08-19 09:38:56 +020014#include <post.h>
15#include <flash.h>
16#include <mtd/cfi_flash.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020017
18DECLARE_GLOBAL_DATA_PTR;
19
Sascha Lauef14ae412010-08-19 09:38:56 +020020static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
Stefan Roeseb765ffb2007-06-15 08:18:01 +020021
Stefan Roese3ad63872007-08-21 16:27:57 +020022ulong flash_get_size(ulong base, int banknum);
23int misc_init_r_kbd(void);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020024
25int board_early_init_f(void)
26{
27 u32 sdr0_pfc1, sdr0_pfc2;
28 u32 reg;
29
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020030 /* PLB Write pipelining disabled. Denali Core workaround */
Stefan Roese5e7abce2010-09-11 09:31:43 +020031 mtdcr(PLB4A0_ACR, 0xDE000000);
32 mtdcr(PLB4A1_ACR, 0xDE000000);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020033
34 /*--------------------------------------------------------------------
35 * Setup the interrupt controller polarities, triggers, etc.
36 *-------------------------------------------------------------------*/
Stefan Roese952e7762009-09-24 09:55:50 +020037 mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
38 mtdcr(UIC0ER, 0x00000000); /* disable all */
39 mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
40 mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
41 mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
42 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
43 mtdcr(UIC0SR, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020044
Stefan Roese952e7762009-09-24 09:55:50 +020045 mtdcr(UIC1SR, 0xffffffff); /* clear all */
46 mtdcr(UIC1ER, 0x00000000); /* disable all */
47 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
48 mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
49 mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
50 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
51 mtdcr(UIC1SR, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020052
Stefan Roese952e7762009-09-24 09:55:50 +020053 mtdcr(UIC2SR, 0xffffffff); /* clear all */
54 mtdcr(UIC2ER, 0x00000000); /* disable all */
55 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
56 mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
57 mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
58 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
59 mtdcr(UIC2SR, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020060
61 /* Trace Pins are disabled. SDR0_PFC0 Register */
62 mtsdr(SDR0_PFC0, 0x0);
63
64 /* select Ethernet pins */
65 mfsdr(SDR0_PFC1, sdr0_pfc1);
66 /* SMII via ZMII */
67 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
68 SDR0_PFC1_SELECT_CONFIG_6;
69 mfsdr(SDR0_PFC2, sdr0_pfc2);
70 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
71 SDR0_PFC2_SELECT_CONFIG_6;
72
73 /* enable SPI (SCP) */
74 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
75
76 mtsdr(SDR0_PFC2, sdr0_pfc2);
77 mtsdr(SDR0_PFC1, sdr0_pfc1);
78
79 mtsdr(SDR0_PFC4, 0x80000000);
80
81 /* PCI arbiter disabled */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020082 /* PCI Host Configuration disbaled */
Stefan Roesed1c3b272009-09-09 16:25:29 +020083 mfsdr(SDR0_PCI0, reg);
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020084 reg = 0;
Stefan Roesed1c3b272009-09-09 16:25:29 +020085 mtsdr(SDR0_PCI0, 0x00000000 | reg);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020086
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
Sascha Lauef14ae412010-08-19 09:38:56 +020090 /* enable the LSB transmitter */
91 gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
92 /* enable the CAN transmitter */
93 gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010094
95 reg = 0; /* reuse as counter */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
97 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
98 & ~CONFIG_SYS_DSPIC_TEST_MASK);
Sascha Lauef14ae412010-08-19 09:38:56 +020099 while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100100 udelay(1000);
101 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100103 /* set "boot error" flag */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
105 in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
106 CONFIG_SYS_DSPIC_TEST_MASK);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100107 }
108#endif
109
Stefan Roese54fd6c92007-11-13 08:18:20 +0100110 /*
111 * Reset PHY's:
112 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
113 * upon reset, and with the first reset upon powerup, the addresses are
114 * not latched reliable, since the IRQ line is multiplexed with an
115 * MDIO address. A 2nd reset at this time will make sure, that the
116 * correct address is latched.
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
119 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
Stefan Roese54fd6c92007-11-13 08:18:20 +0100120 udelay(1000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
122 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
Stefan Roese54fd6c92007-11-13 08:18:20 +0100123 udelay(1000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
125 gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
Stefan Roese54fd6c92007-11-13 08:18:20 +0100126
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200127 return 0;
128}
129
Sascha Lauef14ae412010-08-19 09:38:56 +0200130/*
131 * Override weak default with board specific version
132 */
133phys_addr_t cfi_flash_bank_addr(int bank)
134{
135 return lwmon5_cfi_flash_bank_addr[bank];
136}
137
138/*
139 * Override the weak default mapping function with a board specific one
140 */
141u32 flash_get_bank_size(int cs, int idx)
142{
143 return flash_info[idx].size;
144}
145
146int board_early_init_r(void)
147{
148 u32 val0, val1;
149
150 /*
151 * lwmon5 is manufactured in 2 different board versions:
152 * The lwmon5a board has 64MiB NOR flash instead of the
153 * 128MiB of the original lwmon5. Unfortunately the CFI driver
154 * will report 2 banks of 64MiB even for the smaller flash
155 * chip, since the bank is mirrored. To fix this, we bring
156 * one bank into CFI query mode and read its response. This
157 * enables us to detect the real number of flash devices/
158 * banks which will be used later on by the common CFI driver.
159 */
160
161 /* Put bank 0 into CFI command mode and read */
162 out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
163 val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
164 val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
165
166 /* Reset flash again out of query mode */
167 out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
168
169 /* When not identical, we have 2 different flash devices/banks */
170 if (val0 != val1)
171 return 0;
172
173 /*
174 * Now we're sure that we're running on a LWMON5a board with
175 * only 64MiB NOR flash in one bank:
176 *
177 * Set flash base address and bank count for CFI driver probing.
178 */
179 cfi_flash_num_flash_banks = 1;
180 lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
181
182 return 0;
183}
184
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200185int misc_init_r(void)
186{
187 u32 pbcr;
188 int size_val = 0;
189 u32 reg;
Stefan Roesef47b0482013-03-08 16:50:41 +0100190#ifndef CONFIG_LCD4_LWMON5
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200191 unsigned long usb2d0cr = 0;
192 unsigned long usb2phy0cr, usb2h0cr = 0;
Sascha Lauef14ae412010-08-19 09:38:56 +0200193 unsigned long sdr0_pfc1, sdr0_srst;
Stefan Roesef47b0482013-03-08 16:50:41 +0100194#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200195
196 /*
197 * FLASH stuff...
198 */
199
200 /* Re-do sizing to get full correct info */
201
202 /* adjust flash start and offset */
203 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
204 gd->bd->bi_flashoffset = 0;
205
Stefan Roesed1c3b272009-09-09 16:25:29 +0200206 mfebc(PB0CR, pbcr);
Sascha Lauef14ae412010-08-19 09:38:56 +0200207 size_val = ffs(gd->bd->bi_flashsize) - 21;
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200208 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200209 mtebc(PB0CR, pbcr);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200210
211 /*
212 * Re-check to get correct base address
213 */
214 flash_get_size(gd->bd->bi_flashstart, 0);
215
216 /* Monitor protection ON by default */
Sascha Lauef14ae412010-08-19 09:38:56 +0200217 flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
218 &flash_info[cfi_flash_num_flash_banks - 1]);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200219
220 /* Env protection ON by default */
Sascha Lauef14ae412010-08-19 09:38:56 +0200221 flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
222 CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
223 &flash_info[cfi_flash_num_flash_banks - 1]);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200224
Stefan Roesef47b0482013-03-08 16:50:41 +0100225#ifndef CONFIG_LCD4_LWMON5
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200226 /*
227 * USB suff...
228 */
Sascha Lauef14ae412010-08-19 09:38:56 +0200229
230 /* Reset USB */
231 /* Reset of USB2PHY0 must be active at least 10 us */
232 mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
233 udelay(2000);
234
235 mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
236 SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
237 SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
238 udelay(2000);
239
240 /* Errata CHIP_6 */
241
242 /* 1. Set internal PHY configuration */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200243 /* SDR Setting */
244 mfsdr(SDR0_PFC1, sdr0_pfc1);
245 mfsdr(SDR0_USB0, usb2d0cr);
246 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
247 mfsdr(SDR0_USB2H0CR, usb2h0cr);
248
Sascha Lauef14ae412010-08-19 09:38:56 +0200249 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
250 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
251 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
252 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
253 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
254 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
255 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
256 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
257 usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
258 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200259
Sascha Lauef14ae412010-08-19 09:38:56 +0200260 /*
261 * An 8-bit/60MHz interface is the only possible alternative
262 * when connecting the Device to the PHY
263 */
264 usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
265 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200266
267 mtsdr(SDR0_PFC1, sdr0_pfc1);
268 mtsdr(SDR0_USB0, usb2d0cr);
269 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
270 mtsdr(SDR0_USB2H0CR, usb2h0cr);
271
Sascha Lauef14ae412010-08-19 09:38:56 +0200272 /* 2. De-assert internal PHY reset */
273 mfsdr(SDR0_SRST1, sdr0_srst);
274 sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
275 mtsdr(SDR0_SRST1, sdr0_srst);
276
277 /* 3. Wait for more than 1 ms */
278 udelay(2000);
279
280 /* 4. De-assert USB 2.0 Host main reset */
281 mfsdr(SDR0_SRST0, sdr0_srst);
282 sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
283 mtsdr(SDR0_SRST0, sdr0_srst);
284 udelay(1000);
285
286 /* 5. De-assert reset of OPB2 cores */
287 mfsdr(SDR0_SRST1, sdr0_srst);
288 sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
289 sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
290 sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
291 mtsdr(SDR0_SRST1, sdr0_srst);
292 udelay(1000);
293
294 /* 6. Set EHCI Configure FLAG */
295
296 /* 7. Reassert internal PHY reset: */
297 mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
298 udelay(1000);
Stefan Roesef47b0482013-03-08 16:50:41 +0100299#endif
Sascha Lauef14ae412010-08-19 09:38:56 +0200300
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200301 /*
302 * Clear resets
303 */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200304 mtsdr(SDR0_SRST1, 0x00000000);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200305 mtsdr(SDR0_SRST0, 0x00000000);
306
Stefan Roesef47b0482013-03-08 16:50:41 +0100307#ifndef CONFIG_LCD4_LWMON5
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200308 printf("USB: Host(int phy) Device(ext phy)\n");
Stefan Roesef47b0482013-03-08 16:50:41 +0100309#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200310
311 /*
312 * Clear PLB4A0_ACR[WRP]
313 * This fix will make the MAL burst disabling patch for the Linux
314 * EMAC driver obsolete.
315 */
Stefan Roese5e7abce2010-09-11 09:31:43 +0200316 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
317 mtdcr(PLB4A0_ACR, reg);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200318
Stefan Roesef47b0482013-03-08 16:50:41 +0100319#ifndef CONFIG_LCD4_LWMON5
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200320 /*
Stefan Roese3ad63872007-08-21 16:27:57 +0200321 * Init matrix keyboard
322 */
323 misc_init_r_kbd();
Stefan Roesef47b0482013-03-08 16:50:41 +0100324#endif
Stefan Roese3ad63872007-08-21 16:27:57 +0200325
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200326 return 0;
327}
328
329int checkboard(void)
330{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000331 char buf[64];
332 int i = getenv_f("serial#", buf, sizeof(buf));
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200333
Stefan Roesef47b0482013-03-08 16:50:41 +0100334 printf("Board: %s", __stringify(CONFIG_HOSTNAME));
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200335
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000336 if (i > 0) {
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200337 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000338 puts(buf);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200339 }
340 putc('\n');
341
342 return (0);
343}
344
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200345void hw_watchdog_reset(void)
346{
347 int val;
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200348#if defined(CONFIG_WD_MAX_RATE)
349 unsigned long long ct = get_ticks();
350
351 /*
352 * Don't allow watch-dog triggering more frequently than
353 * the predefined value CONFIG_WD_MAX_RATE [ticks].
354 */
Simon Glassa0d3c822012-12-13 20:49:03 +0000355 if (ct >= gd->arch.wdt_last) {
356 if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200357 return;
358 } else {
359 /* Time base counter had been reset */
Simon Glassa0d3c822012-12-13 20:49:03 +0000360 if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200361 CONFIG_WD_MAX_RATE)
362 return;
363 }
Simon Glassa0d3c822012-12-13 20:49:03 +0000364 gd->arch.wdt_last = get_ticks();
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200365#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200366
367 /*
368 * Toggle watchdog output
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370 val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
371 gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200372}
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200373
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200374int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200375{
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200376 if (argc < 2)
377 return cmd_usage(cmdtp);
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200378
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200379 if ((strcmp(argv[1], "on") == 0))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200381 else if ((strcmp(argv[1], "off") == 0))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382 gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
Wolfgang Denk47e26b12010-07-17 01:06:04 +0200383 else
384 return cmd_usage(cmdtp);
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200385
386 return 0;
387}
388
389U_BOOT_CMD(
390 eepromwp, 2, 0, do_eeprom_wp,
Peter Tyser2fb26042009-01-27 18:03:12 -0600391 "eeprom write protect off/on",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200392 "<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200393);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100394
395#if defined(CONFIG_VIDEO)
396#include <video_fb.h>
397#include <mb862xx.h>
398
399extern GraphicDevice mb862xx;
400
Sascha Lauef14ae412010-08-19 09:38:56 +0200401static const gdc_regs init_regs [] = {
402 { 0x0100, 0x00000f00 },
403 { 0x0020, 0x801401df },
404 { 0x0024, 0x00000000 },
405 { 0x0028, 0x00000000 },
406 { 0x002c, 0x00000000 },
407 { 0x0110, 0x00000000 },
408 { 0x0114, 0x00000000 },
409 { 0x0118, 0x01df0280 },
410 { 0x0004, 0x031f0000 },
411 { 0x0008, 0x027f027f },
412 { 0x000c, 0x015f028f },
413 { 0x0010, 0x020c0000 },
414 { 0x0014, 0x01df01ea },
415 { 0x0018, 0x00000000 },
416 { 0x001c, 0x01e00280 },
417 { 0x0100, 0x80010f00 },
418 { 0x0, 0x0 }
Anatolij Gustschind610a602008-01-11 15:31:09 +0100419};
420
Sascha Lauef14ae412010-08-19 09:38:56 +0200421const gdc_regs *board_get_regs(void)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100422{
423 return init_regs;
424}
425
426/* Returns Lime base address */
Sascha Lauef14ae412010-08-19 09:38:56 +0200427unsigned int board_video_init(void)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100428{
429 /*
430 * Reset Lime controller
431 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100433 udelay(500);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100435
Anatolij Gustschind610a602008-01-11 15:31:09 +0100436 mb862xx.winSizeX = 640;
437 mb862xx.winSizeY = 480;
438 mb862xx.gdfBytesPP = 2;
439 mb862xx.gdfIndex = GDF_15BIT_555RGB;
440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441 return CONFIG_SYS_LIME_BASE_0;
Anatolij Gustschind610a602008-01-11 15:31:09 +0100442}
443
Sascha Lauef14ae412010-08-19 09:38:56 +0200444#define DEFAULT_BRIGHTNESS 0x64
Yuri Tikhonov0f855a12008-03-18 13:27:57 +0100445
446static void board_backlight_brightness(int brightness)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100447{
Yuri Tikhonov0f855a12008-03-18 13:27:57 +0100448 if (brightness > 0) {
Anatolij Gustschind610a602008-01-11 15:31:09 +0100449 /* pwm duty, lamp on */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
451 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100452 } else {
453 /* lamp off */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
455 out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100456 }
457}
458
Sascha Lauef14ae412010-08-19 09:38:56 +0200459void board_backlight_switch(int flag)
Yuri Tikhonov0f855a12008-03-18 13:27:57 +0100460{
461 char * param;
462 int rc;
463
464 if (flag) {
465 param = getenv("brightness");
466 rc = param ? simple_strtol(param, NULL, 10) : -1;
467 if (rc < 0)
468 rc = DEFAULT_BRIGHTNESS;
469 } else {
470 rc = 0;
471 }
472 board_backlight_brightness(rc);
473}
474
Anatolij Gustschind610a602008-01-11 15:31:09 +0100475#if defined(CONFIG_CONSOLE_EXTRA_INFO)
476/*
477 * Return text to be printed besides the logo.
478 */
Sascha Lauef14ae412010-08-19 09:38:56 +0200479void video_get_info_str(int line_number, char *info)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100480{
Sascha Lauef14ae412010-08-19 09:38:56 +0200481 if (line_number == 1)
482 strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
483 else
Anatolij Gustschind610a602008-01-11 15:31:09 +0100484 info [0] = '\0';
Anatolij Gustschind610a602008-01-11 15:31:09 +0100485}
Sascha Lauef14ae412010-08-19 09:38:56 +0200486#endif /* CONFIG_CONSOLE_EXTRA_INFO */
Anatolij Gustschind610a602008-01-11 15:31:09 +0100487#endif /* CONFIG_VIDEO */
Yuri Tikhonovff818b22008-02-04 17:11:53 +0100488
489void board_reset(void)
490{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491 gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
Yuri Tikhonovff818b22008-02-04 17:11:53 +0100492}
Stefan Roesef47b0482013-03-08 16:50:41 +0100493
494#ifdef CONFIG_SPL_OS_BOOT
495/*
496 * lwmon5 specific implementation of spl_start_uboot()
497 *
498 * RETURN
499 * 0 if booting into OS is selected (default)
500 * 1 if booting into U-Boot is selected
501 */
502int spl_start_uboot(void)
503{
504 char s[8];
505
506 env_init();
507 getenv_f("boot_os", s, sizeof(s));
508 if ((s != NULL) && (strcmp(s, "yes") == 0))
509 return 0;
510
511 return 1;
512}
513
514/*
515 * This function is called from the SPL U-Boot version for
516 * early init stuff, that needs to be done for OS (e.g. Linux)
517 * booting. Doing it later in the real U-Boot would not work
518 * in case that the SPL U-Boot boots Linux directly.
519 */
520void spl_board_init(void)
521{
522 const gdc_regs *regs = board_get_regs();
523
524 /*
525 * Setup PFC registers, mainly for ethernet support
526 * later on in Linux
527 */
528 board_early_init_f();
529
Stefan Roese9055f662013-08-26 12:08:48 +0200530 /* enable the LSB transmitter */
531 gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
532
Stefan Roesef47b0482013-03-08 16:50:41 +0100533 /*
534 * Clear resets
535 */
536 mtsdr(SDR0_SRST1, 0x00000000);
537 mtsdr(SDR0_SRST0, 0x00000000);
538
539 /*
540 * Reset Lime controller
541 */
542 gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
543 udelay(500);
544 gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
545
546 out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
547 udelay(300);
548 out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
549
550 while (regs->index) {
551 out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
552 regs->index, regs->value);
553 regs++;
554 }
555
556 board_backlight_brightness(DEFAULT_BRIGHTNESS);
557}
558#endif