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Stefano Babic649a33e2010-11-30 11:46:56 -05001/*
2 * (C) Copyright 2010
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
4 *
5 * Based on da850evm.c, original Copyrights follow:
6 *
7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * Based on da830evm.c. Original Copyrights follow:
10 *
11 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
12 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <common.h>
30#include <i2c.h>
31#include <net.h>
32#include <netdev.h>
33#include <asm/arch/hardware.h>
34#include <asm/arch/emif_defs.h>
35#include <asm/arch/emac_defs.h>
36#include <asm/io.h>
37#include <asm/arch/davinci_misc.h>
38
39DECLARE_GLOBAL_DATA_PTR;
40
41#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
42
43/* SPI0 pin muxer settings */
44static const struct pinmux_config spi1_pins[] = {
45 { pinmux(5), 1, 1 },
46 { pinmux(5), 1, 2 },
47 { pinmux(5), 1, 4 },
48 { pinmux(5), 1, 5 }
49};
50
51/* UART pin muxer settings */
52static const struct pinmux_config uart_pins[] = {
53 { pinmux(0), 4, 6 },
54 { pinmux(0), 4, 7 },
55 { pinmux(4), 2, 4 },
56 { pinmux(4), 2, 5 }
57};
58
59#ifdef CONFIG_DRIVER_TI_EMAC
60#define HAS_RMII 1
61static const struct pinmux_config emac_pins[] = {
62 { pinmux(14), 8, 2 },
63 { pinmux(14), 8, 3 },
64 { pinmux(14), 8, 4 },
65 { pinmux(14), 8, 5 },
66 { pinmux(14), 8, 6 },
67 { pinmux(14), 8, 7 },
68 { pinmux(15), 8, 1 },
69 { pinmux(4), 8, 0 },
70 { pinmux(4), 8, 1 }
71};
72#endif
73
74#ifdef CONFIG_NAND_DAVINCI
75const struct pinmux_config nand_pins[] = {
76 { pinmux(7), 1, 1 },
77 { pinmux(7), 1, 2 },
78 { pinmux(7), 1, 4 },
79 { pinmux(7), 1, 5 },
80 { pinmux(9), 1, 0 },
81 { pinmux(9), 1, 1 },
82 { pinmux(9), 1, 2 },
83 { pinmux(9), 1, 3 },
84 { pinmux(9), 1, 4 },
85 { pinmux(9), 1, 5 },
86 { pinmux(9), 1, 6 },
87 { pinmux(9), 1, 7 },
88 { pinmux(12), 1, 5 },
89 { pinmux(12), 1, 6 }
90};
91#endif
92
93static const struct pinmux_resource pinmuxes[] = {
94#ifdef CONFIG_SPI_FLASH
95 PINMUX_ITEM(spi1_pins),
96#endif
97 PINMUX_ITEM(uart_pins),
98#ifdef CONFIG_NAND_DAVINCI
99 PINMUX_ITEM(nand_pins),
100#endif
101};
102
103static const struct lpsc_resource lpsc[] = {
104 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
105 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
106 { DAVINCI_LPSC_EMAC }, /* image download */
107 { DAVINCI_LPSC_UART2 }, /* console */
108 { DAVINCI_LPSC_GPIO },
109};
110
111int board_init(void)
112{
113#ifndef CONFIG_USE_IRQ
114 irq_init();
115#endif
116
117
118#ifdef CONFIG_NAND_DAVINCI
119 /*
120 * NAND CS setup - cycle counts based on da850evm NAND timings in the
121 * Linux kernel @ 25MHz EMIFA
122 */
123 writel((DAVINCI_ABCR_WSETUP(0) |
124 DAVINCI_ABCR_WSTROBE(0) |
125 DAVINCI_ABCR_WHOLD(0) |
126 DAVINCI_ABCR_RSETUP(0) |
127 DAVINCI_ABCR_RSTROBE(1) |
128 DAVINCI_ABCR_RHOLD(0) |
129 DAVINCI_ABCR_TA(0) |
130 DAVINCI_ABCR_ASIZE_8BIT),
131 &davinci_emif_regs->ab2cr); /* CS3 */
132#endif
133
134 /* arch number of the board */
135 gd->bd->bi_arch_number = MACH_TYPE_EA20;
136
137 /* address of boot parameters */
138 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
139
140 /*
141 * Power on required peripherals
142 * ARM does not have access by default to PSC0 and PSC1
143 * assuming here that the DSP bootloader has set the IOPU
144 * such that PSC access is available to ARM
145 */
146 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
147 return 1;
148
149 /* setup the SUSPSRC for ARM to control emulation suspend */
150 writel(readl(&davinci_syscfg_regs->suspsrc) &
151 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
152 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
153 DAVINCI_SYSCFG_SUSPSRC_UART2),
154 &davinci_syscfg_regs->suspsrc);
155
156 /* configure pinmux settings */
157 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
158 return 1;
159
160#ifdef CONFIG_DRIVER_TI_EMAC
161 if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
162 return 1;
163
164 davinci_emac_mii_mode_sel(HAS_RMII);
165#endif /* CONFIG_DRIVER_TI_EMAC */
166
167 /* enable the console UART */
168 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
169 DAVINCI_UART_PWREMU_MGMT_UTRST),
170 &davinci_uart2_ctrl_regs->pwremu_mgmt);
171
172 return 0;
173}
174
175#ifdef CONFIG_DRIVER_TI_EMAC
176
177/*
178 * Initializes on-board ethernet controllers.
179 */
180int board_eth_init(bd_t *bis)
181{
182 if (!davinci_emac_initialize()) {
183 printf("Error: Ethernet init failed!\n");
184 return -1;
185 }
186
187 /*
188 * This board has a RMII PHY. However, the MDC line on the SOM
189 * must not be disabled (there is no MII PHY on the
190 * baseboard) via the GPIO2[6], because this pin
191 * disables at the same time the SPI flash.
192 */
193
194 return 0;
195}
196#endif /* CONFIG_DRIVER_TI_EMAC */