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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IOCON 1 /* on a IoCon board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME iocon
Dirk Eibach28437152013-06-26 16:04:31 +020020#define CONFIG_IDENT_STRING " iocon 0.05"
Dirk Eibacha605ea72010-10-21 10:50:05 +020021#include "amcc-common.h"
22
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000023#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibacha605ea72010-10-21 10:50:05 +020025#define CONFIG_LAST_STAGE_INIT
26
27#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
28
29/*
30 * Configure PLL
31 */
32#define PLLMR0_DEFAULT PLLMR0_266_133_66
33#define PLLMR1_DEFAULT PLLMR1_266_133_66
34
Dirk Eibach996d88d2012-04-26 03:54:25 +000035#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
36#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
37#define CONFIG_AUTOBOOT_STOP_STR " "
38
Dirk Eibacha605ea72010-10-21 10:50:05 +020039/* new uImage format support */
40#define CONFIG_FIT
41#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
42
43#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
44
45/*
46 * Default environment variables
47 */
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4 /* PHY address */
58#define CONFIG_HAS_ETH0
59#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
60
61/*
62 * Commands additional to the ones defined in amcc-common.h
63 */
64#define CONFIG_CMD_CACHE
Michal Simekd0db28f2014-05-02 13:34:21 +020065#define CONFIG_CMD_FPGA
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +053066#define CONFIG_CMD_FPGA_LOADMK
Dirk Eibacha605ea72010-10-21 10:50:05 +020067#undef CONFIG_CMD_EEPROM
68
69/*
70 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
71 */
72#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
73
74/* SDRAM timings used in datasheet */
75#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
76#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
77#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
78#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
79#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
80
81/*
82 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
83 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
84 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
85 * The Linux BASE_BAUD define should match this configuration.
86 * baseBaud = cpuClock/(uartDivisor*16)
87 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
88 * set Linux BASE_BAUD to 403200.
89 */
90#define CONFIG_CONS_INDEX 1 /* Use UART0 */
91#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
92#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
93#define CONFIG_SYS_BASE_BAUD 691200
94
95/*
96 * I2C stuff
97 */
Heiko Schocherea818db2013-01-29 08:53:15 +010098#define CONFIG_SYS_I2C
Dirk Eibach880540d2013-04-25 02:40:01 +000099#define CONFIG_SYS_I2C_PPC4XX
100#define CONFIG_SYS_I2C_PPC4XX_CH0
101#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
102#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibacha605ea72010-10-21 10:50:05 +0200103
Dirk Eibache50e8962013-07-25 19:28:13 +0200104#define CONFIG_SYS_I2C_SPEED 400000
105
106#define CONFIG_PCA953X /* NXP PCA9554 */
107#define CONFIG_PCA9698 /* NXP PCA9698 */
108
Dirk Eibacha605ea72010-10-21 10:50:05 +0200109/*
110 * Software (bit-bang) I2C driver configuration
111 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200112#define CONFIG_SYS_I2C_SOFT
113#define CONFIG_SYS_I2C_SOFT_SPEED 50000
114#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
115#define I2C_SOFT_DECLARATIONS2
116#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
117#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
118#define I2C_SOFT_DECLARATIONS3
119#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
120#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
121#define I2C_SOFT_DECLARATIONS4
122#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
123#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
124
125#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
Dirk Eibacha605ea72010-10-21 10:50:05 +0200126
127#ifndef __ASSEMBLY__
Dirk Eibache50e8962013-07-25 19:28:13 +0200128void fpga_gpio_set(unsigned int bus, int pin);
129void fpga_gpio_clear(unsigned int bus, int pin);
130int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200131#endif
132
133#define I2C_ACTIVE { }
134#define I2C_TRISTATE { }
Dirk Eibache50e8962013-07-25 19:28:13 +0200135#define I2C_READ \
136 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
137#define I2C_SDA(bit) \
138 do { \
139 if (bit) \
140 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
141 else \
142 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
143 } while (0)
144#define I2C_SCL(bit) \
145 do { \
146 if (bit) \
147 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
148 else \
149 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
150 } while (0)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200151#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
152
153/*
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100154 * OSD hardware
155 */
156#define CONFIG_SYS_MPC92469AC
157#define CONFIG_SYS_CH7301
158
159/*
Dirk Eibacha605ea72010-10-21 10:50:05 +0200160 * FLASH organization
161 */
162#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
163#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
164
165#define CONFIG_SYS_FLASH_BASE 0xFC000000
166#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
167
168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
169#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
170
171#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
172#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
173
174#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200175
176#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
177#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
178
179#ifdef CONFIG_ENV_IS_IN_FLASH
180#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
181#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
182#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
183
184/* Address and size of Redundant Environment Sector */
185#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
186#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
187#endif
188
189/*
190 * PPC405 GPIO Configuration
191 */
192#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
193{ \
194/* GPIO Core 0 */ \
195{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
196{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
197{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
198{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
199{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
200{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
201{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
202{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
204{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
205{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
207{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
208{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
210{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
211{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
212{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
213{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
214{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
215{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
216{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
217{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
218{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
219{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
220{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
221{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
222{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
223{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
224{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
225{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
226{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
227} \
228}
229
230/*
231 * Definitions for initial stack pointer and data area (in data cache)
232 */
233/* use on chip memory (OCM) for temperary stack until sdram is tested */
234#define CONFIG_SYS_TEMP_STACK_OCM 1
235
236/* On Chip Memory location */
237#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
238#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
239#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
240#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
241
Dirk Eibacha605ea72010-10-21 10:50:05 +0200242#define CONFIG_SYS_GBL_DATA_OFFSET \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900243 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200244#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
245
246/*
247 * External Bus Controller (EBC) Setup
248 */
249
250/* Memory Bank 0 (NOR-FLASH) initialization */
251#define CONFIG_SYS_EBC_PB0AP 0xa382a880
252#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
253
254/* Memory Bank 1 (NVRAM) initializatio */
255#define CONFIG_SYS_EBC_PB1AP 0x92015480
256#define CONFIG_SYS_EBC_PB1CR 0xFB858000
257
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100258/* Memory Bank 2 (FPGA0) initialization */
259#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200260#define CONFIG_SYS_EBC_PB2AP 0x02825080
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100261#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200262
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100263#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
264#define CONFIG_SYS_FPGA_DONE(k) 0x0010
265
266#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200267
Dirk Eibache50e8962013-07-25 19:28:13 +0200268#define CONFIG_SYS_MCLINK_MAX 3
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200269
Dirk Eibache50e8962013-07-25 19:28:13 +0200270#define CONFIG_SYS_FPGA_PTR \
271 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200272
Dirk Eibacha605ea72010-10-21 10:50:05 +0200273/* Memory Bank 3 (Latches) initialization */
274#define CONFIG_SYS_LATCH_BASE 0x7f200000
275#define CONFIG_SYS_EBC_PB3AP 0x02025080
276#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
277
278#define CONFIG_SYS_LATCH0_RESET 0xffef
279#define CONFIG_SYS_LATCH0_BOOT 0xffff
280#define CONFIG_SYS_LATCH1_RESET 0xffff
281#define CONFIG_SYS_LATCH1_BOOT 0xffff
282
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100283/*
284 * OSD Setup
285 */
286#define CONFIG_SYS_MPC92469AC
287#define CONFIG_SYS_CH7301
Dirk Eibache50e8962013-07-25 19:28:13 +0200288#define CONFIG_SYS_OSD_SCREENS 1
289
290#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
291#define CONFIG_BITBANGMII_MULTI
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100292
Dirk Eibacha605ea72010-10-21 10:50:05 +0200293#endif /* __CONFIG_H */