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Masahiro Yamada4fb96c42016-10-08 13:25:31 +09001/*
2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
Simon Glass9d922452017-05-17 17:18:03 -06009#include <dm.h>
Masahiro Yamada4fb96c42016-10-08 13:25:31 +090010#include <reset-uclass.h>
Masahiro Yamada4fb96c42016-10-08 13:25:31 +090011#include <linux/bitops.h>
12#include <linux/io.h>
13#include <linux/sizes.h>
14
15struct uniphier_reset_data {
16 unsigned int id;
17 unsigned int reg;
18 unsigned int bit;
19 unsigned int flags;
20#define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
21};
22
23#define UNIPHIER_RESET_ID_END (unsigned int)(-1)
24
25#define UNIPHIER_RESET_END \
26 { .id = UNIPHIER_RESET_ID_END }
27
28#define UNIPHIER_RESET(_id, _reg, _bit) \
29 { \
30 .id = (_id), \
31 .reg = (_reg), \
32 .bit = (_bit), \
33 }
34
35#define UNIPHIER_RESETX(_id, _reg, _bit) \
36 { \
37 .id = (_id), \
38 .reg = (_reg), \
39 .bit = (_bit), \
40 .flags = UNIPHIER_RESET_ACTIVE_LOW, \
41 }
42
43/* System reset data */
Masahiro Yamada1d21e1b2017-06-22 16:42:04 +090044static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
Masahiro Yamada6584b1e2017-08-13 09:01:16 +090045 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
46 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
47 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
48 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
49 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
Masahiro Yamada4fb96c42016-10-08 13:25:31 +090050 UNIPHIER_RESET_END,
51};
52
Masahiro Yamada1d21e1b2017-06-22 16:42:04 +090053static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
Masahiro Yamada6584b1e2017-08-13 09:01:16 +090054 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
55 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
56 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
57 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
Masahiro Yamada4fb96c42016-10-08 13:25:31 +090058 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
59 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
60 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
61 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */
62 UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */
63 UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */
64 UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */
65 UNIPHIER_RESET_END,
66};
67
Masahiro Yamada1d21e1b2017-06-22 16:42:04 +090068static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
Masahiro Yamada6584b1e2017-08-13 09:01:16 +090069 UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
70 UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
71 UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */
72 UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */
Masahiro Yamada4fb96c42016-10-08 13:25:31 +090073 UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
74 UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
75 UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
76 UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */
77 UNIPHIER_RESET_END,
78};
79
80/* Media I/O reset data */
81#define UNIPHIER_MIO_RESET_SD(id, ch) \
82 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
83
84#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \
85 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26)
86
87#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \
88 UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0)
89
90#define UNIPHIER_MIO_RESET_USB2(id, ch) \
91 UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0)
92
93#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \
94 UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24)
95
96#define UNIPHIER_MIO_RESET_DMAC(id) \
97 UNIPHIER_RESETX((id), 0x110, 17)
98
Masahiro Yamada1d21e1b2017-06-22 16:42:04 +090099static const struct uniphier_reset_data uniphier_mio_reset_data[] = {
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900100 UNIPHIER_MIO_RESET_SD(0, 0),
101 UNIPHIER_MIO_RESET_SD(1, 1),
102 UNIPHIER_MIO_RESET_SD(2, 2),
103 UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0),
104 UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1),
105 UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2),
106 UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1),
107 UNIPHIER_MIO_RESET_DMAC(7),
108 UNIPHIER_MIO_RESET_USB2(8, 0),
109 UNIPHIER_MIO_RESET_USB2(9, 1),
110 UNIPHIER_MIO_RESET_USB2(10, 2),
111 UNIPHIER_MIO_RESET_USB2(11, 3),
112 UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0),
113 UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1),
114 UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2),
115 UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3),
116 UNIPHIER_RESET_END,
117};
118
119/* Peripheral reset data */
120#define UNIPHIER_PERI_RESET_UART(id, ch) \
121 UNIPHIER_RESETX((id), 0x114, 19 + (ch))
122
123#define UNIPHIER_PERI_RESET_I2C(id, ch) \
124 UNIPHIER_RESETX((id), 0x114, 5 + (ch))
125
126#define UNIPHIER_PERI_RESET_FI2C(id, ch) \
127 UNIPHIER_RESETX((id), 0x114, 24 + (ch))
128
Masahiro Yamada1d21e1b2017-06-22 16:42:04 +0900129static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900130 UNIPHIER_PERI_RESET_UART(0, 0),
131 UNIPHIER_PERI_RESET_UART(1, 1),
132 UNIPHIER_PERI_RESET_UART(2, 2),
133 UNIPHIER_PERI_RESET_UART(3, 3),
134 UNIPHIER_PERI_RESET_I2C(4, 0),
135 UNIPHIER_PERI_RESET_I2C(5, 1),
136 UNIPHIER_PERI_RESET_I2C(6, 2),
137 UNIPHIER_PERI_RESET_I2C(7, 3),
138 UNIPHIER_PERI_RESET_I2C(8, 4),
139 UNIPHIER_RESET_END,
140};
141
Masahiro Yamada1d21e1b2017-06-22 16:42:04 +0900142static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = {
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900143 UNIPHIER_PERI_RESET_UART(0, 0),
144 UNIPHIER_PERI_RESET_UART(1, 1),
145 UNIPHIER_PERI_RESET_UART(2, 2),
146 UNIPHIER_PERI_RESET_UART(3, 3),
147 UNIPHIER_PERI_RESET_FI2C(4, 0),
148 UNIPHIER_PERI_RESET_FI2C(5, 1),
149 UNIPHIER_PERI_RESET_FI2C(6, 2),
150 UNIPHIER_PERI_RESET_FI2C(7, 3),
151 UNIPHIER_PERI_RESET_FI2C(8, 4),
152 UNIPHIER_PERI_RESET_FI2C(9, 5),
153 UNIPHIER_PERI_RESET_FI2C(10, 6),
154 UNIPHIER_RESET_END,
155};
156
157/* core implementaton */
158struct uniphier_reset_priv {
159 void __iomem *base;
160 const struct uniphier_reset_data *data;
161};
162
163static int uniphier_reset_request(struct reset_ctl *reset_ctl)
164{
165 return 0;
166}
167
168static int uniphier_reset_free(struct reset_ctl *reset_ctl)
169{
170 return 0;
171}
172
173static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert)
174{
175 struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev);
176 unsigned long id = reset_ctl->id;
177 const struct uniphier_reset_data *p;
178
179 for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) {
180 u32 mask, val;
181
182 if (p->id != id)
183 continue;
184
185 val = readl(priv->base + p->reg);
186
187 if (p->flags & UNIPHIER_RESET_ACTIVE_LOW)
188 assert = !assert;
189
190 mask = BIT(p->bit);
191
192 if (assert)
193 val |= mask;
194 else
195 val &= ~mask;
196
197 writel(val, priv->base + p->reg);
198
199 return 0;
200 }
201
202 dev_err(priv->dev, "reset_id=%lu was not handled\n", id);
203 return -EINVAL;
204}
205
206static int uniphier_reset_assert(struct reset_ctl *reset_ctl)
207{
208 return uniphier_reset_update(reset_ctl, 1);
209}
210
211static int uniphier_reset_deassert(struct reset_ctl *reset_ctl)
212{
213 return uniphier_reset_update(reset_ctl, 0);
214}
215
216static const struct reset_ops uniphier_reset_ops = {
217 .request = uniphier_reset_request,
218 .free = uniphier_reset_free,
219 .rst_assert = uniphier_reset_assert,
220 .rst_deassert = uniphier_reset_deassert,
221};
222
223static int uniphier_reset_probe(struct udevice *dev)
224{
225 struct uniphier_reset_priv *priv = dev_get_priv(dev);
226 fdt_addr_t addr;
227
Simon Glassa821c4a2017-05-17 17:18:05 -0600228 addr = devfdt_get_addr(dev->parent);
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900229 if (addr == FDT_ADDR_T_NONE)
230 return -EINVAL;
231
232 priv->base = devm_ioremap(dev, addr, SZ_4K);
233 if (!priv->base)
234 return -ENOMEM;
235
236 priv->data = (void *)dev_get_driver_data(dev);
237
238 return 0;
239}
240
241static const struct udevice_id uniphier_reset_match[] = {
242 /* System reset */
243 {
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900244 .compatible = "socionext,uniphier-ld4-reset",
Masahiro Yamada6584b1e2017-08-13 09:01:16 +0900245 .data = (ulong)uniphier_pro4_sys_reset_data,
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900246 },
247 {
248 .compatible = "socionext,uniphier-pro4-reset",
249 .data = (ulong)uniphier_pro4_sys_reset_data,
250 },
251 {
252 .compatible = "socionext,uniphier-sld8-reset",
Masahiro Yamada6584b1e2017-08-13 09:01:16 +0900253 .data = (ulong)uniphier_pro4_sys_reset_data,
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900254 },
255 {
256 .compatible = "socionext,uniphier-pro5-reset",
Masahiro Yamada6584b1e2017-08-13 09:01:16 +0900257 .data = (ulong)uniphier_pro4_sys_reset_data,
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900258 },
259 {
260 .compatible = "socionext,uniphier-pxs2-reset",
261 .data = (ulong)uniphier_pxs2_sys_reset_data,
262 },
263 {
264 .compatible = "socionext,uniphier-ld11-reset",
Masahiro Yamada6584b1e2017-08-13 09:01:16 +0900265 .data = (ulong)uniphier_ld20_sys_reset_data,
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900266 },
267 {
268 .compatible = "socionext,uniphier-ld20-reset",
269 .data = (ulong)uniphier_ld20_sys_reset_data,
270 },
271 /* Media I/O reset */
272 {
Masahiro Yamada4fb96c42016-10-08 13:25:31 +0900273 .compatible = "socionext,uniphier-ld4-mio-reset",
274 .data = (ulong)uniphier_mio_reset_data,
275 },
276 {
277 .compatible = "socionext,uniphier-pro4-mio-reset",
278 .data = (ulong)uniphier_mio_reset_data,
279 },
280 {
281 .compatible = "socionext,uniphier-sld8-mio-reset",
282 .data = (ulong)uniphier_mio_reset_data,
283 },
284 {
285 .compatible = "socionext,uniphier-pro5-mio-reset",
286 .data = (ulong)uniphier_mio_reset_data,
287 },
288 {
289 .compatible = "socionext,uniphier-pxs2-mio-reset",
290 .data = (ulong)uniphier_mio_reset_data,
291 },
292 {
293 .compatible = "socionext,uniphier-ld11-mio-reset",
294 .data = (ulong)uniphier_mio_reset_data,
295 },
296 {
297 .compatible = "socionext,uniphier-ld20-mio-reset",
298 .data = (ulong)uniphier_mio_reset_data,
299 },
300 /* Peripheral reset */
301 {
302 .compatible = "socionext,uniphier-ld4-peri-reset",
303 .data = (ulong)uniphier_ld4_peri_reset_data,
304 },
305 {
306 .compatible = "socionext,uniphier-pro4-peri-reset",
307 .data = (ulong)uniphier_pro4_peri_reset_data,
308 },
309 {
310 .compatible = "socionext,uniphier-sld8-peri-reset",
311 .data = (ulong)uniphier_ld4_peri_reset_data,
312 },
313 {
314 .compatible = "socionext,uniphier-pro5-peri-reset",
315 .data = (ulong)uniphier_pro4_peri_reset_data,
316 },
317 {
318 .compatible = "socionext,uniphier-pxs2-peri-reset",
319 .data = (ulong)uniphier_pro4_peri_reset_data,
320 },
321 {
322 .compatible = "socionext,uniphier-ld11-peri-reset",
323 .data = (ulong)uniphier_pro4_peri_reset_data,
324 },
325 {
326 .compatible = "socionext,uniphier-ld20-peri-reset",
327 .data = (ulong)uniphier_pro4_peri_reset_data,
328 },
329 { /* sentinel */ }
330};
331
332U_BOOT_DRIVER(uniphier_reset) = {
333 .name = "uniphier-reset",
334 .id = UCLASS_RESET,
335 .of_match = uniphier_reset_match,
336 .probe = uniphier_reset_probe,
337 .priv_auto_alloc_size = sizeof(struct uniphier_reset_priv),
338 .ops = &uniphier_reset_ops,
339};