| Chris Zankel | c978b52 | 2016-08-10 18:36:44 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Tensilica Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | #ifndef _XTENSA_CACHE_H |
| 7 | #define _XTENSA_CACHE_H |
| 8 | |
| 9 | #include <asm/arch/core.h> |
| 10 | |
| 11 | #define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE |
| 12 | |
| 13 | #ifndef __ASSEMBLY__ |
| 14 | |
| 15 | void __flush_dcache_all(void); |
| 16 | void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size); |
| 17 | void __invalidate_dcache_all(void); |
| 18 | void __invalidate_dcache_range(unsigned long addr, unsigned long size); |
| 19 | |
| 20 | void __invalidate_icache_all(void); |
| 21 | void __invalidate_icache_range(unsigned long addr, unsigned long size); |
| 22 | |
| 23 | #endif |
| 24 | |
| 25 | #endif /* _XTENSA_CACHE_H */ |