Bin Meng | a187559 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 1 | U-Boot config options used in fec_mxc.c |
Troy Kisky | c30eab2 | 2012-10-22 16:40:39 +0000 | [diff] [blame] | 2 | |
| 3 | CONFIG_FEC_MXC |
Olaf Mandel | 95c6922 | 2015-05-28 14:59:18 +0200 | [diff] [blame] | 4 | Selects fec_mxc.c to be compiled into u-boot. Can read out the |
| 5 | ethaddr from the SoC eFuses (see below). |
Troy Kisky | c30eab2 | 2012-10-22 16:40:39 +0000 | [diff] [blame] | 6 | |
| 7 | CONFIG_MII |
| 8 | Must be defined if CONFIG_FEC_MXC is defined. |
| 9 | |
| 10 | CONFIG_FEC_XCV_TYPE |
| 11 | Defaults to MII100 for 100 Base-tx. |
| 12 | RGMII selects 1000 Base-tx reduced pin count interface. |
| 13 | RMII selects 100 Base-tx reduced pin count interface. |
| 14 | |
| 15 | CONFIG_FEC_MXC_SWAP_PACKET |
| 16 | Forced on iff MX28. |
| 17 | Swaps the bytes order of all words(4 byte units) in the packet. |
| 18 | This should not be specified by a board file. It is cpu specific. |
| 19 | |
| 20 | CONFIG_PHYLIB |
| 21 | fec_mxc supports PHYLIB and should be used for new boards. |
| 22 | |
| 23 | CONFIG_FEC_MXC_NO_ANEG |
| 24 | Relevant only if PHYLIB not used. Skips auto-negotiation restart. |
| 25 | |
| 26 | CONFIG_FEC_MXC_PHYADDR |
| 27 | Optional, selects the exact phy address that should be connected |
| 28 | and function fecmxc_initialize will try to initialize it. |
Olaf Mandel | 95c6922 | 2015-05-28 14:59:18 +0200 | [diff] [blame] | 29 | |
Hannes Schmelzer | 0750701 | 2016-06-22 12:07:14 +0200 | [diff] [blame] | 30 | CONFIG_FEC_FIXED_SPEED |
| 31 | Optional, selects a fixed speed on the MAC interface without asking some |
| 32 | phy. This is usefull if there is a direct MAC <-> MAC connection, for |
| 33 | example if the CPU is connected directly via the RGMII interface to a |
| 34 | ethernet-switch. |
Olaf Mandel | 95c6922 | 2015-05-28 14:59:18 +0200 | [diff] [blame] | 35 | |
| 36 | Reading the ethaddr from the SoC eFuses: |
| 37 | if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the |
| 38 | ethaddr variable, then its value gets read from the corresponding eFuses in |
| 39 | the SoC. See the README files of the specific SoC for details. |