| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010-2012 | ||||
| 4 | * NVIDIA Corporation <www.nvidia.com> | ||||
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 5 | */ |
| 6 | |||||
| Tom Warren | bfcf46d | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 7 | #ifndef _TEGRA_COMMON_H_ |
| 8 | #define _TEGRA_COMMON_H_ | ||||
| Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 9 | #include <linux/sizes.h> |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 10 | #include <linux/stringify.h> |
| 11 | |||||
| 12 | /* | ||||
| 13 | * High Level Configuration Options | ||||
| 14 | */ | ||||
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 15 | |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 16 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
| 17 | |||||
| Thierry Reding | f41f0a1 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 18 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
| 19 | #ifndef CONFIG_ARM64 | ||||
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 20 | #define CFG_SYS_TIMER_RATE 1000000 |
| 21 | #define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE | ||||
| Thierry Reding | f41f0a1 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 22 | #endif |
| Rob Herring | 31df989 | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 23 | |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 24 | /* Environment */ |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 25 | |
| 26 | /* | ||||
| Tom Warren | bfcf46d | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 27 | * NS16550 Configuration |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 28 | */ |
| Tom Rini | 9109213 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 29 | #define CFG_SYS_NS16550_CLK V_NS16550_CLK |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 30 | |
| Peter Robinson | 632fb97 | 2020-04-02 00:28:54 +0100 | [diff] [blame] | 31 | #ifdef CONFIG_ARM64 |
| 32 | #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" | ||||
| 33 | #else | ||||
| 34 | #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" | ||||
| 35 | #endif | ||||
| 36 | |||||
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 37 | /*----------------------------------------------------------------------- |
| 38 | * Physical Memory Map | ||||
| 39 | */ | ||||
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 40 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
| 41 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ | ||||
| 42 | |||||
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 43 | #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 44 | |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 45 | #define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 46 | |
| Stephen Warren | f097532 | 2017-12-19 18:30:37 -0700 | [diff] [blame] | 47 | #ifndef CONFIG_ARM64 |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame^] | 48 | #define CFG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| 49 | #define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN | ||||
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 50 | |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 51 | /* Defines for SPL */ |
| Stephen Warren | 0d1bd15 | 2017-12-19 18:30:35 -0700 | [diff] [blame] | 52 | #endif |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 53 | |
| Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 54 | #endif /* _TEGRA_COMMON_H_ */ |