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wdenk42d1f032003-10-15 23:53:47 +00001/*
Andy Fleming61a21e92007-08-14 01:34:21 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * Copyright(c) 2003 Motorola Inc.
wdenk42d1f032003-10-15 23:53:47 +00004 */
5
6#ifndef __MPC85xx_H__
7#define __MPC85xx_H__
8
wdenk42d1f032003-10-15 23:53:47 +00009#if defined(CONFIG_E500)
10#include <e500.h>
11#endif
12
wdenk0ac6f8b2004-07-09 23:27:13 +000013/*
14 * SCCR - System Clock Control Register, 9-8
wdenk42d1f032003-10-15 23:53:47 +000015 */
wdenk0ac6f8b2004-07-09 23:27:13 +000016#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
17#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
wdenk42d1f032003-10-15 23:53:47 +000018#define SCCR_DFBRG_SHIFT 0
19
wdenk0ac6f8b2004-07-09 23:27:13 +000020#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
21#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
22#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
23#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
wdenk42d1f032003-10-15 23:53:47 +000024
Timur Tabie46fedf2011-08-04 18:03:41 -050025/*
26 * Define default values for some CCSR macros to make header files cleaner*
27 *
28 * To completely disable CCSR relocation in a board header file, define
Tom Rini65cc0e22022-11-16 13:10:41 -050029 * CONFIG_SPL_SYS_CCSR_DO_NOT_RELOCATE. This will force CFG_SYS_CCSRBAR_PHYS
30 * to a value that is the same as CFG_SYS_CCSRBAR.
Timur Tabie46fedf2011-08-04 18:03:41 -050031 */
32
Tom Rini65cc0e22022-11-16 13:10:41 -050033#ifdef CFG_SYS_CCSRBAR_PHYS
34#error "Do not define CFG_SYS_CCSRBAR_PHYS directly. Use \
35CFG_SYS_CCSRBAR_PHYS_LOW and/or CFG_SYS_CCSRBAR_PHYS_HIGH instead."
Timur Tabie46fedf2011-08-04 18:03:41 -050036#endif
37
Tom Rini6074a532022-05-21 11:26:27 -040038#if CONFIG_IS_ENABLED(SYS_CCSR_DO_NOT_RELOCATE)
Tom Rini65cc0e22022-11-16 13:10:41 -050039#undef CFG_SYS_CCSRBAR_PHYS_HIGH
40#undef CFG_SYS_CCSRBAR_PHYS_LOW
41#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
Timur Tabie46fedf2011-08-04 18:03:41 -050042#endif
43
Tom Rini65cc0e22022-11-16 13:10:41 -050044#ifndef CFG_SYS_CCSRBAR
45#define CFG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
Timur Tabie46fedf2011-08-04 18:03:41 -050046#endif
47
Tom Rini65cc0e22022-11-16 13:10:41 -050048#ifndef CFG_SYS_CCSRBAR_PHYS_HIGH
Timur Tabie46fedf2011-08-04 18:03:41 -050049#ifdef CONFIG_PHYS_64BIT
Tom Rini65cc0e22022-11-16 13:10:41 -050050#define CFG_SYS_CCSRBAR_PHYS_HIGH 0xf
Timur Tabie46fedf2011-08-04 18:03:41 -050051#else
Tom Rini65cc0e22022-11-16 13:10:41 -050052#define CFG_SYS_CCSRBAR_PHYS_HIGH 0
Timur Tabie46fedf2011-08-04 18:03:41 -050053#endif
54#endif
55
Tom Rini65cc0e22022-11-16 13:10:41 -050056#ifndef CFG_SYS_CCSRBAR_PHYS_LOW
57#define CFG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
Timur Tabie46fedf2011-08-04 18:03:41 -050058#endif
59
Tom Rini65cc0e22022-11-16 13:10:41 -050060#define CFG_SYS_CCSRBAR_PHYS ((CFG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
61 CFG_SYS_CCSRBAR_PHYS_LOW)
Timur Tabie46fedf2011-08-04 18:03:41 -050062
wdenk42d1f032003-10-15 23:53:47 +000063#endif /* __MPC85xx_H__ */