blob: 09cd45d3744154722d39dd4f5c1cb8dbe3fe2570 [file] [log] [blame]
Rob Herring37fc0ed2011-10-24 08:50:20 +00001/*
2 * Copyright 2010-2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <common.h>
19#include <ahci.h>
Rob Herringbd0d90e2012-02-21 12:52:26 +000020#include <netdev.h>
Rob Herring37fc0ed2011-10-24 08:50:20 +000021#include <scsi.h>
22
23#include <asm/sizes.h>
Rob Herring877012d2012-02-01 16:57:54 +000024#include <asm/io.h>
Rob Herring37fc0ed2011-10-24 08:50:20 +000025
Rob Herring0c34e692012-02-01 16:57:55 +000026#define HB_SREG_A9_PWR_REQ 0xfff3cf00
Rob Herring4a3ea212012-02-01 16:57:57 +000027#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
Rob Herring0c34e692012-02-01 16:57:55 +000028#define HB_PWR_SUSPEND 0
29#define HB_PWR_SOFT_RESET 1
30#define HB_PWR_HARD_RESET 2
31#define HB_PWR_SHUTDOWN 3
32
Rob Herring37fc0ed2011-10-24 08:50:20 +000033DECLARE_GLOBAL_DATA_PTR;
34
35/*
36 * Miscellaneous platform dependent initialisations
37 */
38int board_init(void)
39{
40 icache_enable();
41
42 return 0;
43}
44
Rob Herring9a420982011-12-15 11:15:50 +000045/* We know all the init functions have been run now */
46int board_eth_init(bd_t *bis)
47{
48 int rc = 0;
49
50#ifdef CONFIG_CALXEDA_XGMAC
51 rc += calxedaxgmac_initialize(0, 0xfff50000);
52 rc += calxedaxgmac_initialize(1, 0xfff51000);
53#endif
54 return rc;
55}
56
Rob Herring37fc0ed2011-10-24 08:50:20 +000057int misc_init_r(void)
58{
Rob Herring4a3ea212012-02-01 16:57:57 +000059 char envbuffer[16];
60 u32 boot_choice;
61
Rob Herring37fc0ed2011-10-24 08:50:20 +000062 ahci_init(0xffe08000);
63 scsi_scan(1);
Rob Herring4a3ea212012-02-01 16:57:57 +000064
65 boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
66 sprintf(envbuffer, "bootcmd%d", boot_choice);
67 if (getenv(envbuffer)) {
68 sprintf(envbuffer, "run bootcmd%d", boot_choice);
69 setenv("bootcmd", envbuffer);
70 } else
71 setenv("bootcmd", "");
72
Rob Herring37fc0ed2011-10-24 08:50:20 +000073 return 0;
74}
75
76int dram_init(void)
77{
78 gd->ram_size = SZ_512M;
79 return 0;
80}
81
82void dram_init_banksize(void)
83{
84 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
85 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
86}
87
88void reset_cpu(ulong addr)
89{
Rob Herring0c34e692012-02-01 16:57:55 +000090 writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
Rob Herring5bedf882012-12-02 17:06:22 +000091
92 wfi();
Rob Herring37fc0ed2011-10-24 08:50:20 +000093}