blob: a0fe15e86e600b1f8f0d796eac23314ebea56589 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8540ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8540 1 /* MPC8540 specific */
42#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
wdenk42d1f032003-10-15 23:53:47 +000043
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044/*
45 * default CCARBAR is at 0xff700000
46 * assume U-Boot is less than 0.5MB
47 */
48#define CONFIG_SYS_TEXT_BASE 0xfff80000
49
Jon Loeliger288693a2005-07-25 12:14:54 -050050#ifndef CONFIG_HAS_FEC
51#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
52#endif
53
wdenk0ac6f8b2004-07-09 23:27:13 +000054#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050055#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000057#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060058#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk42d1f032003-10-15 23:53:47 +000059
wdenk0ac6f8b2004-07-09 23:27:13 +000060/*
61 * sysclk for MPC85xx
62 *
63 * Two valid values are:
64 * 33000000
65 * 66000000
66 *
67 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000068 * is likely the desired value here, so that is now the default.
69 * The board, however, can run at 66MHz. In any event, this value
70 * must match the settings of some switches. Details can be found
71 * in the README.mpc85xxads.
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050072 *
73 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
74 * 33MHz to accommodate, based on a PCI pin.
75 * Note that PCI-X won't work at 33MHz.
wdenk0ac6f8b2004-07-09 23:27:13 +000076 */
77
wdenk9aea9532004-08-01 23:02:45 +000078#ifndef CONFIG_SYS_CLK_FREQ
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050079#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000080#endif
81
wdenk9aea9532004-08-01 23:02:45 +000082
wdenk0ac6f8b2004-07-09 23:27:13 +000083/*
84 * These can be toggled for performance analysis, otherwise use default.
85 */
86#define CONFIG_L2_CACHE /* toggle L2 cache */
87#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
90#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000091
Timur Tabie46fedf2011-08-04 18:03:41 -050092#define CONFIG_SYS_CCSRBAR 0xe0000000
93#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000094
Kumar Gala9617c8d2008-06-06 13:12:18 -050095/* DDR Setup */
96#define CONFIG_FSL_DDR1
97#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
98#define CONFIG_DDR_SPD
99#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +0000100
Kumar Gala9617c8d2008-06-06 13:12:18 -0500101#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
104#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000105
Kumar Gala9617c8d2008-06-06 13:12:18 -0500106#define CONFIG_NUM_DDR_CONTROLLERS 1
107#define CONFIG_DIMM_SLOTS_PER_CTLR 1
108#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +0000109
Kumar Gala9617c8d2008-06-06 13:12:18 -0500110/* I2C addresses of SPD EEPROMs */
111#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +0000112
Kumar Gala9617c8d2008-06-06 13:12:18 -0500113/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
115#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
116#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
117#define CONFIG_SYS_DDR_TIMING_1 0x37344321
118#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
119#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
120#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
121#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000122
wdenk0ac6f8b2004-07-09 23:27:13 +0000123/*
124 * SDRAM on the Local Bus
125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
127#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
130#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
135#undef CONFIG_SYS_FLASH_CHECKSUM
136#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000138
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
142#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000143#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000145#endif
146
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200147#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_CFI
149#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000150
wdenk42d1f032003-10-15 23:53:47 +0000151#undef CONFIG_CLOCKS_IN_MHZ
152
wdenk0ac6f8b2004-07-09 23:27:13 +0000153
154/*
155 * Local Bus Definitions
156 */
157
158/*
159 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000161 *
162 * For BR2, need:
163 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
164 * port-size = 32-bits = BR2[19:20] = 11
165 * no parity checking = BR2[21:22] = 00
166 * SDRAM for MSEL = BR2[24:26] = 011
167 * Valid = BR[31] = 1
168 *
169 * 0 4 8 12 16 20 24 28
170 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
171 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000173 * FIXME: the top 17 bits of BR2.
174 */
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000177
178/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000180 *
181 * For OR2, need:
182 * 64MB mask for AM, OR2[0:7] = 1111 1100
183 * XAM, OR2[17:18] = 11
184 * 9 columns OR2[19-21] = 010
185 * 13 rows OR2[23-25] = 100
186 * EAD set for extra time OR[31] = 1
187 *
188 * 0 4 8 12 16 20 24 28
189 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
190 */
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
195#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
196#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
197#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000198
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500199#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
200 | LSDMR_RFCR5 \
201 | LSDMR_PRETOACT3 \
202 | LSDMR_ACTTORW3 \
203 | LSDMR_BL8 \
204 | LSDMR_WRC2 \
205 | LSDMR_CL3 \
206 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000207 )
208
209/*
210 * SDRAM Controller configuration sequence.
211 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500212#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
213#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
214#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
215#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
216#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000217
wdenk42d1f032003-10-15 23:53:47 +0000218
wdenk9aea9532004-08-01 23:02:45 +0000219/*
220 * 32KB, 8-bit wide for ADS config reg
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BR4_PRELIM 0xf8000801
223#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
224#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_INIT_RAM_LOCK 1
227#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200228#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000229
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200230#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
234#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000235
236/* Serial Port */
237#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_NS16550
239#define CONFIG_SYS_NS16550_SERIAL
240#define CONFIG_SYS_NS16550_REG_SIZE 1
241#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
247#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000248
249/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_HUSH_PARSER
251#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000252#endif
253
Matthew McClintock0e163872006-06-28 10:43:36 -0500254/* pass open firmware flat tree */
Kumar Gala0fd5ec62007-11-28 22:54:27 -0600255#define CONFIG_OF_LIBFDT 1
256#define CONFIG_OF_BOARD_SETUP 1
257#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500258
Jon Loeliger20476722006-10-20 15:50:15 -0500259/*
260 * I2C
261 */
262#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
263#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000264#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
266#define CONFIG_SYS_I2C_SLAVE 0x7F
267#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
268#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk42d1f032003-10-15 23:53:47 +0000269
wdenk0ac6f8b2004-07-09 23:27:13 +0000270/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600271#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600272#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600273#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000275
276/*
277 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300278 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000279 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600280#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600281#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600282#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600284#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600285#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
287#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000288
wdenk42d1f032003-10-15 23:53:47 +0000289#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000290
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200291#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000292
wdenk42d1f032003-10-15 23:53:47 +0000293#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000294#undef CONFIG_TULIP
295
296#if !defined(CONFIG_PCI_PNP)
297 #define PCI_ENET0_IOADDR 0xe0000000
298 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200299 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000300#endif
301
wdenk0ac6f8b2004-07-09 23:27:13 +0000302#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000304
305#endif /* CONFIG_PCI */
306
307
308#if defined(CONFIG_TSEC_ENET)
309
wdenk0ac6f8b2004-07-09 23:27:13 +0000310#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500311#define CONFIG_TSEC1 1
312#define CONFIG_TSEC1_NAME "TSEC0"
313#define CONFIG_TSEC2 1
314#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000315#define TSEC1_PHY_ADDR 0
316#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000317#define TSEC1_PHYIDX 0
318#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500319#define TSEC1_FLAGS TSEC_GIGABIT
320#define TSEC2_FLAGS TSEC_GIGABIT
wdenk9aea9532004-08-01 23:02:45 +0000321
Jon Loeliger288693a2005-07-25 12:14:54 -0500322
323#if CONFIG_HAS_FEC
wdenk9aea9532004-08-01 23:02:45 +0000324#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500325#define CONFIG_MPC85XX_FEC_NAME "FEC"
wdenk9aea9532004-08-01 23:02:45 +0000326#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000327#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500328#define FEC_FLAGS 0
Jon Loeliger288693a2005-07-25 12:14:54 -0500329#endif
wdenk9aea9532004-08-01 23:02:45 +0000330
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500331/* Options are: TSEC[0-1], FEC */
332#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000333
334#endif /* CONFIG_TSEC_ENET */
335
336
337/*
338 * Environment
339 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200341 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200343 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
344 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000345#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200347 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200349 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000350#endif
351
wdenk0ac6f8b2004-07-09 23:27:13 +0000352#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000354
Jon Loeliger2835e512007-06-13 13:22:08 -0500355
356/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500357 * BOOTP options
358 */
359#define CONFIG_BOOTP_BOOTFILESIZE
360#define CONFIG_BOOTP_BOOTPATH
361#define CONFIG_BOOTP_GATEWAY
362#define CONFIG_BOOTP_HOSTNAME
363
364
365/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500366 * Command line configuration.
367 */
368#include <config_cmd_default.h>
369
370#define CONFIG_CMD_PING
371#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600372#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500373#define CONFIG_CMD_IRQ
374#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500375
376#if defined(CONFIG_PCI)
377 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000378#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500381 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500382 #undef CONFIG_CMD_LOADS
383#endif
384
wdenk42d1f032003-10-15 23:53:47 +0000385
wdenk0ac6f8b2004-07-09 23:27:13 +0000386#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000387
388/*
389 * Miscellaneous configurable options
390 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500392#define CONFIG_CMDLINE_EDITING /* Command-line editing */
393#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
395#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk0ac6f8b2004-07-09 23:27:13 +0000396
Jon Loeliger2835e512007-06-13 13:22:08 -0500397#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000399#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000401#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
404#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
405#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
406#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000407
408/*
409 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500410 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000411 * the maximum mapped by the Linux kernel during initialization.
412 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500413#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
414#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000415
Jon Loeliger2835e512007-06-13 13:22:08 -0500416#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000417#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
418#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
419#endif
420
wdenk9aea9532004-08-01 23:02:45 +0000421
422/*
423 * Environment Configuration
424 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000425
426/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000427#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500428#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000429#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000430#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000431#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000432#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000433#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
wdenk42d1f032003-10-15 23:53:47 +0000434#endif
435
wdenk0ac6f8b2004-07-09 23:27:13 +0000436#define CONFIG_IPADDR 192.168.1.253
437
438#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000439#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000440#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000441
442#define CONFIG_SERVERIP 192.168.1.1
443#define CONFIG_GATEWAYIP 192.168.1.1
444#define CONFIG_NETMASK 255.255.255.0
445
446#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
447
448#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
449#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
450
451#define CONFIG_BAUDRATE 115200
452
wdenk9aea9532004-08-01 23:02:45 +0000453#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000454 "netdev=eth0\0" \
455 "consoledev=ttyS0\0" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500456 "ramdiskaddr=1000000\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500457 "ramdiskfile=your.ramdisk.u-boot\0" \
458 "fdtaddr=400000\0" \
459 "fdtfile=your.fdt.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000460
wdenk9aea9532004-08-01 23:02:45 +0000461#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000462 "setenv bootargs root=/dev/nfs rw " \
463 "nfsroot=$serverip:$rootpath " \
464 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
465 "console=$consoledev,$baudrate $othbootargs;" \
466 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500467 "tftp $fdtaddr $fdtfile;" \
468 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000469
470#define CONFIG_RAMBOOTCOMMAND \
471 "setenv bootargs root=/dev/ram rw " \
472 "console=$consoledev,$baudrate $othbootargs;" \
473 "tftp $ramdiskaddr $ramdiskfile;" \
474 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500475 "tftp $fdtaddr $fdtfile;" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500476 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000477
478#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000479
480#endif /* __CONFIG_H */