blob: 4a656bb51bf42a86886b9cc0f44ff227ac38fa86 [file] [log] [blame]
Tom Warrenf01b6312012-12-11 13:34:18 +00001/*
2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __TEGRA_COMMON_H
25#define __TEGRA_COMMON_H
26#include <asm/sizes.h>
27#include <linux/stringify.h>
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
33#define CONFIG_TEGRA /* which is a Tegra generic machine */
34#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
35
36#define CONFIG_SYS_CACHELINE_SIZE 32
37
38#include <asm/arch/tegra.h> /* get chip and board defs */
39
40/*
41 * Display CPU and Board information
42 */
43#define CONFIG_DISPLAY_CPUINFO
44#define CONFIG_DISPLAY_BOARDINFO
45
46#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
47#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
48
49/* Environment */
50#define CONFIG_ENV_VARS_UBOOT_CONFIG
51#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
52
53/*
54 * Size of malloc() pool
55 */
56#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
57
58/*
59 * PllX Configuration
60 */
61#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
62
63#define CONFIG_SYS_NS16550
64#define CONFIG_SYS_NS16550_SERIAL
65#define CONFIG_SYS_NS16550_REG_SIZE (-4)
66#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
67
68/*
69 * select serial console configuration
70 */
71#define CONFIG_CONS_INDEX 1
72
73/* allow to overwrite serial and ethaddr */
74#define CONFIG_ENV_OVERWRITE
75#define CONFIG_BAUDRATE 115200
76
77/* include default commands */
78#include <config_cmd_default.h>
79
80/* remove unused commands */
81#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
82#undef CONFIG_CMD_FPGA /* FPGA configuration support */
83#undef CONFIG_CMD_IMI
84#undef CONFIG_CMD_IMLS
85#undef CONFIG_CMD_NFS /* NFS support */
86#undef CONFIG_CMD_NET /* network support */
87
88/* turn on command-line edit/hist/auto */
89#define CONFIG_CMDLINE_EDITING
90#define CONFIG_COMMAND_HISTORY
91#define CONFIG_AUTO_COMPLETE
92
93#define CONFIG_SYS_NO_FLASH
94
95#define CONFIG_CONSOLE_MUX
96#define CONFIG_SYS_CONSOLE_IS_IN_ENV
97#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
98
99/*
100 * Miscellaneous configurable options
101 */
102#define CONFIG_SYS_LONGHELP /* undef to save memory */
103#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
104#define CONFIG_SYS_PROMPT V_PROMPT
105/*
106 * Increasing the size of the IO buffer as default nfsargs size is more
107 * than 256 and so it is not possible to edit it
108 */
109#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
110/* Print Buffer Size */
111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
112 sizeof(CONFIG_SYS_PROMPT) + 16)
113#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114/* Boot Argument Buffer Size */
115#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
116
117#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
118#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
119
120#define CONFIG_SYS_HZ 1000
121
122/*-----------------------------------------------------------------------
123 * Physical Memory Map
124 */
125#define CONFIG_NR_DRAM_BANKS 1
126#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
127#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
128
129#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
130#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
131
132#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
133
134#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
135#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
136#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
137 CONFIG_SYS_INIT_RAM_SIZE - \
138 GENERATED_GBL_DATA_SIZE)
139
140#define CONFIG_TEGRA_GPIO
141#define CONFIG_CMD_GPIO
142#define CONFIG_CMD_ENTERRCM
143#define CONFIG_CMD_BOOTZ
144
145/* Defines for SPL */
146#define CONFIG_SPL
147#define CONFIG_SPL_FRAMEWORK
148#define CONFIG_SPL_RAM_DEVICE
149#define CONFIG_SPL_BOARD_INIT
150#define CONFIG_SPL_NAND_SIMPLE
151#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
152 CONFIG_SPL_TEXT_BASE)
153#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
154
155#define CONFIG_SPL_LIBCOMMON_SUPPORT
156#define CONFIG_SPL_LIBGENERIC_SUPPORT
157#define CONFIG_SPL_SERIAL_SUPPORT
158#define CONFIG_SPL_GPIO_SUPPORT
159
160#endif /* _TEGRA_COMMON_H_ */