blob: 714352b1cda17133c4a2508d5e877537da4c90cb [file] [log] [blame]
Mike Frysingerd4d77302008-02-04 19:26:55 -05001/*
2 * blackfin-config-pre.h - common defines for Blackfin boards in config.h
3 *
4 * Copyright (c) 2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
10#define __ASM_BLACKFIN_CONFIG_PRE_H__
11
12/* Misc helper functions */
13#define XMK_STR(x) #x
14#define MK_STR(x) XMK_STR(x)
15#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
16
17/* Configurable Blackfin-specific monitor commands */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020018#define CONFIG_SYS_BFIN_CMD_BOOTLDR 0x01
19#define CONFIG_SYS_BFIN_CMD_CPLBINFO 0x02
20#define CONFIG_SYS_BFIN_CMD_OTP 0x04
21#define CONFIG_SYS_BFIN_CMD_CACHE_DUMP 0x08
Mike Frysingerd4d77302008-02-04 19:26:55 -050022
Mike Frysinger30fb9d22008-08-07 13:17:03 -040023/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
Mike Frysingerd4d77302008-02-04 19:26:55 -050024 * Depending on your cpu, some of these may not be valid, check your HRM.
25 * The actual values here are meaningless as long as they're unique.
26 */
27#define BFIN_BOOT_BYPASS 1 /* bypass bootrom */
28#define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */
29#define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */
30#define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */
31#define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */
32#define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */
33#define BFIN_BOOT_UART 7 /* boot ldr over uart */
34#define BFIN_BOOT_IDLE 8 /* do nothing, just idle */
35#define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */
36#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */
37#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
38#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
Mike Frysinger30fb9d22008-08-07 13:17:03 -040039#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
Mike Frysingerd4d77302008-02-04 19:26:55 -050040
41#endif