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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yangaa89b552016-08-12 17:58:12 +08002/*
3 * Copyright (c) 2016 Rockchip Electronics Co., Ltd
Kever Yangaa89b552016-08-12 17:58:12 +08004 */
5#include <asm/io.h>
Kever Yang15f09a12019-03-28 11:01:23 +08006#include <asm/arch-rockchip/hardware.h>
Kever Yang070e48b2019-03-29 09:09:03 +08007#include <asm/arch-rockchip/grf_rk3288.h>
Kever Yangaa89b552016-08-12 17:58:12 +08008
Kever Yang070e48b2019-03-29 09:09:03 +08009#define GRF_BASE 0xff770000
Kever Yangaa89b552016-08-12 17:58:12 +080010
11int arch_cpu_init(void)
12{
13 /* We do some SoC one time setting here. */
Kever Yang070e48b2019-03-29 09:09:03 +080014 struct rk3288_grf * const grf = (void *)GRF_BASE;
Kever Yangaa89b552016-08-12 17:58:12 +080015
16 /* Use rkpwm by default */
Kever Yang070e48b2019-03-29 09:09:03 +080017 rk_setreg(&grf->soc_con2, 1 << 0);
Kever Yangaa89b552016-08-12 17:58:12 +080018
19 return 0;
20}
Kever Yange83e8852019-03-29 09:09:04 +080021
22#ifdef CONFIG_DEBUG_UART_BOARD_INIT
23void board_debug_uart_init(void)
24{
25 /* Enable early UART on the RK3288 */
26 struct rk3288_grf * const grf = (void *)GRF_BASE;
27
28 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
29 GPIO7C6_MASK << GPIO7C6_SHIFT,
30 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
31 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
32}
33#endif