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Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
3 *
Tom Rini0b179982013-07-24 09:34:30 -04004 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00005 */
6
Paul Burton7a9d1092013-11-09 10:22:08 +00007#ifndef _MALTA_CONFIG_H
8#define _MALTA_CONFIG_H
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00009
10#include <asm/addrspace.h>
11#include <asm/malta.h>
12
13/*
14 * System configuration
15 */
Paul Burton7a9d1092013-11-09 10:22:08 +000016#define CONFIG_MALTA
Paul Burton5f978d72014-04-07 10:11:23 +010017#define CONFIG_SYS_GENERIC_BOARD
18#define CONFIG_BOARD_EARLY_INIT_F
19#define CONFIG_DISPLAY_BOARDINFO
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000020
Gabor Juhosab413052013-10-24 14:32:00 +020021#define CONFIG_MEMSIZE_IN_BYTES
22
Gabor Juhosfeaa6062013-05-22 03:57:42 +000023#define CONFIG_PCI
24#define CONFIG_PCI_GT64120
Paul Burtonbaf37f02013-11-08 11:18:50 +000025#define CONFIG_PCI_MSC01
Gabor Juhosfeaa6062013-05-22 03:57:42 +000026#define CONFIG_PCI_PNP
Gabor Juhosf1957492013-05-22 03:57:44 +000027#define CONFIG_PCNET
Paul Burtone0878af2013-11-08 11:18:52 +000028#define CONFIG_PCNET_79C973
29#define PCNET_HAS_PROM
Gabor Juhosfeaa6062013-05-22 03:57:42 +000030
Paul Burton3ced12a2013-11-08 11:18:55 +000031#define CONFIG_MISC_INIT_R
32#define CONFIG_RTC_MC146818
33#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
34
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000035/*
36 * CPU Configuration
37 */
38#define CONFIG_SYS_MHZ 250 /* arbitrary value */
39#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000040
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000041/*
42 * Memory map
43 */
Gabor Juhos10473d02013-11-12 16:47:32 +010044#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */
45#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000046
47#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
48#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024)
49
50#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
51
52#define CONFIG_SYS_LOAD_ADDR 0x81000000
53#define CONFIG_SYS_MEMTEST_START 0x80100000
54#define CONFIG_SYS_MEMTEST_END 0x80800000
55
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
Paul Burton67d47522013-11-26 17:45:28 +000058#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000059
60/*
61 * Console configuration
62 */
63#if defined(CONFIG_SYS_LITTLE_ENDIAN)
Paul Burton7a9d1092013-11-09 10:22:08 +000064#define CONFIG_SYS_PROMPT "maltael # "
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000065#else
Paul Burton7a9d1092013-11-09 10:22:08 +000066#define CONFIG_SYS_PROMPT "malta # "
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000067#endif
68
69#define CONFIG_SYS_CBSIZE 256
70#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
71 sizeof(CONFIG_SYS_PROMPT) + 16)
72#define CONFIG_SYS_MAXARGS 16
73
Paul Burtona3bdaac2015-01-29 10:38:22 +000074#define CONFIG_SYS_HUSH_PARSER
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000075#define CONFIG_AUTO_COMPLETE
76#define CONFIG_CMDLINE_EDITING
77
78/*
79 * Serial driver
80 */
81#define CONFIG_BAUDRATE 115200
82
83#define CONFIG_SYS_NS16550
84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Burton72117da2013-11-26 17:45:26 +000086#define CONFIG_SYS_NS16550_CLK (115200 * 16)
Paul Burtonbaf37f02013-11-08 11:18:50 +000087#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE)
88#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000089#define CONFIG_CONS_INDEX 1
90
91/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000092 * Flash configuration
93 */
Gabor Juhos52caee02013-05-22 03:57:39 +000094#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE)
95#define CONFIG_SYS_MAX_FLASH_BANKS 1
96#define CONFIG_SYS_MAX_FLASH_SECT 128
97#define CONFIG_SYS_FLASH_CFI
98#define CONFIG_FLASH_CFI_DRIVER
99#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000100
101/*
Paul Burtonfba6f452013-11-08 11:18:56 +0000102 * Environment
103 */
104#define CONFIG_ENV_IS_IN_FLASH
105#define CONFIG_ENV_SECT_SIZE 0x20000
106#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
107#define CONFIG_ENV_ADDR \
108 (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
109
110/*
Paul Burtonba21a452015-01-29 10:38:20 +0000111 * IDE/ATA
112 */
113#define CONFIG_SYS_IDE_MAXBUS 1
114#define CONFIG_SYS_IDE_MAXDEVICE 2
115#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS
116#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0
117#define CONFIG_SYS_ATA_DATA_OFFSET 0
118#define CONFIG_SYS_ATA_REG_OFFSET 0
119
120/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000121 * Commands
122 */
123#include <config_cmd_default.h>
124
125#undef CONFIG_CMD_FPGA
126#undef CONFIG_CMD_LOADB
127#undef CONFIG_CMD_LOADS
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000128#undef CONFIG_CMD_NFS
129
Paul Burton3ced12a2013-11-08 11:18:55 +0000130#define CONFIG_CMD_DATE
Paul Burtone0878af2013-11-08 11:18:52 +0000131#define CONFIG_CMD_DHCP
Paul Burtond4d774e2015-01-29 10:38:23 +0000132#define CONFIG_CMD_ELF
Paul Burtonba21a452015-01-29 10:38:20 +0000133#define CONFIG_CMD_IDE
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000134#define CONFIG_CMD_PCI
Gabor Juhosf1957492013-05-22 03:57:44 +0000135#define CONFIG_CMD_PING
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000136
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000137#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */
138
Paul Burton7a9d1092013-11-09 10:22:08 +0000139#endif /* _MALTA_CONFIG_H */