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ramneek mehresh9dee2052013-08-05 16:00:16 +05301/*
2 * Freescale USB Controller
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
York Sun49d87b12013-08-14 10:56:49 -07006 * SPDX-License-Identifier: GPL-2.0+
ramneek mehresh9dee2052013-08-05 16:00:16 +05307 */
8
9#ifndef _ASM_FSL_USB_H_
10#define _ASM_FSL_USB_H_
11
12#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
13struct ccsr_usb_port_ctrl {
14 u32 ctrl;
15 u32 drvvbuscfg;
16 u32 pwrfltcfg;
17 u32 sts;
18 u8 res_14[0xc];
19 u32 bistcfg;
20 u32 biststs;
21 u32 abistcfg;
22 u32 abiststs;
23 u8 res_30[0x10];
24 u32 xcvrprg;
25 u32 anaprg;
26 u32 anadrv;
27 u32 anasts;
28};
29
30struct ccsr_usb_phy {
31 u32 id;
32 struct ccsr_usb_port_ctrl port1;
33 u8 res_50[0xc];
34 u32 tvr;
35 u32 pllprg[4];
36 u8 res_70[0x4];
37 u32 anaccfg;
38 u32 dbg;
39 u8 res_7c[0x4];
40 struct ccsr_usb_port_ctrl port2;
41 u8 res_dc[0x334];
42};
43
44#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
45#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
46#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
47#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
48#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
49#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
50#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
Nikhil Badolad1c561c2014-04-15 14:44:52 +053051#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
52#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
53#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
54#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
55#endif
ramneek mehresh9dee2052013-08-05 16:00:16 +053056#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
57#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
58#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
59#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
Suresh Gupta9c641a82014-02-26 14:29:12 +053060#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
61#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
62
63#define INC_DCNT_THRESHOLD_25MV (0 << 4)
64#define INC_DCNT_THRESHOLD_50MV (1 << 4)
65#define DEC_DCNT_THRESHOLD_25MV (2 << 4)
66#define DEC_DCNT_THRESHOLD_50MV (3 << 4)
ramneek mehresh9dee2052013-08-05 16:00:16 +053067#else
68struct ccsr_usb_phy {
Suresh Gupta9c641a82014-02-26 14:29:12 +053069 u32 config1;
70 u32 config2;
71 u32 config3;
72 u32 config4;
73 u32 config5;
74 u32 status1;
ramneek mehresh9dee2052013-08-05 16:00:16 +053075 u32 usb_enable_override;
76 u8 res[0xe4];
77};
Suresh Gupta9c641a82014-02-26 14:29:12 +053078#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
79#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
80#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
81#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
82#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
83#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
84#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
85#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
ramneek mehresh9dee2052013-08-05 16:00:16 +053086#endif
87
Nikhil Badolac26c80a2014-09-30 11:22:43 +053088/* USB Erratum Checking code */
89#ifdef CONFIG_PPC
90static inline bool has_erratum_a006261(void)
91{
92 u32 svr = get_svr();
93 u32 soc = SVR_SOC_VER(svr);
94
95 switch (soc) {
96 case SVR_P1010:
97 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
98 case SVR_P2041:
99 case SVR_P2040:
100 return IS_SVR_REV(svr, 1, 0) ||
101 IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
102 case SVR_P3041:
103 return IS_SVR_REV(svr, 1, 0) ||
104 IS_SVR_REV(svr, 1, 1) ||
105 IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
106 case SVR_P5010:
107 case SVR_P5020:
108 case SVR_P5021:
109 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
110 case SVR_T4240:
111 case SVR_T4160:
112 case SVR_T4080:
113 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
114 case SVR_T1040:
115 return IS_SVR_REV(svr, 1, 0);
116 case SVR_T2080:
117 case SVR_T2081:
118 return IS_SVR_REV(svr, 1, 0);
119 case SVR_P5040:
120 return IS_SVR_REV(svr, 1, 0);
121 }
122
123 return false;
124}
125
126static inline bool has_erratum_a007075(void)
127{
128 u32 svr = get_svr();
129 u32 soc = SVR_SOC_VER(svr);
130
131 switch (soc) {
132 case SVR_B4860:
133 case SVR_B4420:
134 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
135 case SVR_P1010:
136 return IS_SVR_REV(svr, 1, 0);
137 case SVR_P4080:
138 return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
139 }
140 return false;
141}
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530142
143static inline bool has_erratum_a007798(void)
144{
145 return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
146 IS_SVR_REV(get_svr(), 2, 0);
147}
Nikhil Badolada5ce442014-10-30 10:11:28 +0530148
149static inline bool has_erratum_a007792(void)
150{
151 u32 svr = get_svr();
152 u32 soc = SVR_SOC_VER(svr);
153
154 switch (soc) {
155 case SVR_T4240:
156 case SVR_T4160:
157 return IS_SVR_REV(svr, 2, 0);
158 case SVR_T1040:
159 return IS_SVR_REV(svr, 1, 0);
160 case SVR_T2080:
161 case SVR_T2081:
162 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
163 }
164 return false;
165}
166
Nikhil Badolac26c80a2014-09-30 11:22:43 +0530167#else
168static inline bool has_erratum_a006261(void)
169{
170 return false;
171}
172
173static inline bool has_erratum_a007075(void)
174{
175 return false;
176}
177
Nikhil Badolaf3dff692014-10-17 09:12:07 +0530178static inline bool has_erratum_a007798(void)
179{
180 return false;
181}
182
Nikhil Badolada5ce442014-10-30 10:11:28 +0530183static inline bool has_erratum_a007792(void)
184{
185 return false;
186}
Nikhil Badolac26c80a2014-09-30 11:22:43 +0530187#endif
ramneek mehresh9dee2052013-08-05 16:00:16 +0530188#endif /*_ASM_FSL_USB_H_ */