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wdenk0f89ba42000-11-16 20:23:11 +00001/*
2 * definitions for MPC8260 I/O Ports
3 *
4 * (in addition to those provided in <asm/immap_8260.h>)
5 *
6 * Murray.Jensen@cmst.csiro.au, 20-Oct-00
7 */
8
9/*
10 * this structure mirrors the layout of the five port registers in
11 * the internal memory map - see iop8260_t in <asm/immap_8260.h>
12 */
13typedef struct {
14 unsigned int pdir; /* Port Data Direction Register (35-3) */
15 unsigned int ppar; /* Port Pin Assignment Register (35-4) */
16 unsigned int psor; /* Port Special Options Register (35-5) */
17 unsigned int podr; /* Port Open Drain Register (35-2) */
18 unsigned int pdat; /* Port Data Register (35-3) */
19} ioport_t;
20
21/*
22 * this macro calculates the address within the internal
23 * memory map (im) of the set of registers for a port (idx)
24 *
25 * the internal memory map aligns the above structure on
26 * a 0x20 byte boundary
27 */
28#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
29
30/*
31 * this structure provides configuration
32 * information for one port pin
33 */
34typedef struct {
35 unsigned char conf:1; /* if 1, configure this port */
36 unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */
37 unsigned char psor:1; /* Port Special Options Register (35-2) */
38 unsigned char pdir:1; /* Port Data Direction Register (35-3) */
39 unsigned char podr:1; /* Port Open Drain Register (35-2) */
40 unsigned char pdat:1; /* Port Data Register (35-2) */
41} iop_conf_t;
42
43/*
44 * a table that contains configuration information for all 32 pins
45 * of all four MPC8260 I/O ports.
46 *
47 * NOTE: in the second dimension of this table, index 0 refers to pin 31
48 * and index 31 refers to pin 0. this made the code in the table look more
49 * like the table in the 8260UM (and in the hymod manuals).
50 */
51extern const iop_conf_t iop_conf_tab[4][32];