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Andy Fleming50586ef2008-10-30 16:47:16 -05001/*
Jerry Huangd621da02011-01-06 23:42:19 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
Andy Fleming50586ef2008-10-30 16:47:16 -05003 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <common.h>
30#include <command.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040031#include <hwconfig.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050032#include <mmc.h>
33#include <part.h>
34#include <malloc.h>
35#include <mmc.h>
36#include <fsl_esdhc.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040037#include <fdt_support.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050038#include <asm/io.h>
39
Andy Fleming50586ef2008-10-30 16:47:16 -050040DECLARE_GLOBAL_DATA_PTR;
41
42struct fsl_esdhc {
43 uint dsaddr;
44 uint blkattr;
45 uint cmdarg;
46 uint xfertyp;
47 uint cmdrsp0;
48 uint cmdrsp1;
49 uint cmdrsp2;
50 uint cmdrsp3;
51 uint datport;
52 uint prsstat;
53 uint proctl;
54 uint sysctl;
55 uint irqstat;
56 uint irqstaten;
57 uint irqsigen;
58 uint autoc12err;
59 uint hostcapblt;
60 uint wml;
Jason Liu46927082011-11-25 00:18:04 +000061 uint mixctrl;
62 char reserved1[4];
Andy Fleming50586ef2008-10-30 16:47:16 -050063 uint fevt;
64 char reserved2[168];
65 uint hostver;
66 char reserved3[780];
67 uint scr;
68};
69
70/* Return the XFERTYP flags for a given command and data packet */
71uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
72{
73 uint xfertyp = 0;
74
75 if (data) {
Dipen Dudhat77c14582009-10-05 15:41:58 +053076 xfertyp |= XFERTYP_DPSEL;
77#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
78 xfertyp |= XFERTYP_DMAEN;
79#endif
Andy Fleming50586ef2008-10-30 16:47:16 -050080 if (data->blocks > 1) {
81 xfertyp |= XFERTYP_MSBSEL;
82 xfertyp |= XFERTYP_BCEN;
Jerry Huangd621da02011-01-06 23:42:19 -060083#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
84 xfertyp |= XFERTYP_AC12EN;
85#endif
Andy Fleming50586ef2008-10-30 16:47:16 -050086 }
87
88 if (data->flags & MMC_DATA_READ)
89 xfertyp |= XFERTYP_DTDSEL;
90 }
91
92 if (cmd->resp_type & MMC_RSP_CRC)
93 xfertyp |= XFERTYP_CCCEN;
94 if (cmd->resp_type & MMC_RSP_OPCODE)
95 xfertyp |= XFERTYP_CICEN;
96 if (cmd->resp_type & MMC_RSP_136)
97 xfertyp |= XFERTYP_RSPTYP_136;
98 else if (cmd->resp_type & MMC_RSP_BUSY)
99 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
100 else if (cmd->resp_type & MMC_RSP_PRESENT)
101 xfertyp |= XFERTYP_RSPTYP_48;
102
Jason Liu4571de32011-03-22 01:32:31 +0000103#ifdef CONFIG_MX53
104 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
105 xfertyp |= XFERTYP_CMDTYP_ABORT;
106#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500107 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
108}
109
Dipen Dudhat77c14582009-10-05 15:41:58 +0530110#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
111/*
112 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
113 */
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200114static void
Dipen Dudhat77c14582009-10-05 15:41:58 +0530115esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
116{
Ira Snyder8eee2bd2011-12-23 08:30:40 +0000117 struct fsl_esdhc_cfg *cfg = mmc->priv;
118 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530119 uint blocks;
120 char *buffer;
121 uint databuf;
122 uint size;
123 uint irqstat;
124 uint timeout;
125
126 if (data->flags & MMC_DATA_READ) {
127 blocks = data->blocks;
128 buffer = data->dest;
129 while (blocks) {
130 timeout = PIO_TIMEOUT;
131 size = data->blocksize;
132 irqstat = esdhc_read32(&regs->irqstat);
133 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
134 && --timeout);
135 if (timeout <= 0) {
136 printf("\nData Read Failed in PIO Mode.");
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200137 return;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530138 }
139 while (size && (!(irqstat & IRQSTAT_TC))) {
140 udelay(100); /* Wait before last byte transfer complete */
141 irqstat = esdhc_read32(&regs->irqstat);
142 databuf = in_le32(&regs->datport);
143 *((uint *)buffer) = databuf;
144 buffer += 4;
145 size -= 4;
146 }
147 blocks--;
148 }
149 } else {
150 blocks = data->blocks;
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200151 buffer = (char *)data->src;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530152 while (blocks) {
153 timeout = PIO_TIMEOUT;
154 size = data->blocksize;
155 irqstat = esdhc_read32(&regs->irqstat);
156 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
157 && --timeout);
158 if (timeout <= 0) {
159 printf("\nData Write Failed in PIO Mode.");
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200160 return;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530161 }
162 while (size && (!(irqstat & IRQSTAT_TC))) {
163 udelay(100); /* Wait before last byte transfer complete */
164 databuf = *((uint *)buffer);
165 buffer += 4;
166 size -= 4;
167 irqstat = esdhc_read32(&regs->irqstat);
168 out_le32(&regs->datport, databuf);
169 }
170 blocks--;
171 }
172 }
173}
174#endif
175
Andy Fleming50586ef2008-10-30 16:47:16 -0500176static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
177{
Andy Fleming50586ef2008-10-30 16:47:16 -0500178 int timeout;
Stefano Babicc67bee12010-02-05 15:11:27 +0100179 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
180 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200181#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
182 uint wml_value;
Andy Fleming50586ef2008-10-30 16:47:16 -0500183
184 wml_value = data->blocksize/4;
185
186 if (data->flags & MMC_DATA_READ) {
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530187 if (wml_value > WML_RD_WML_MAX)
188 wml_value = WML_RD_WML_MAX_VAL;
Andy Fleming50586ef2008-10-30 16:47:16 -0500189
Roy Zangab467c52010-02-09 18:23:33 +0800190 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
Stefano Babicc67bee12010-02-05 15:11:27 +0100191 esdhc_write32(&regs->dsaddr, (u32)data->dest);
Andy Fleming50586ef2008-10-30 16:47:16 -0500192 } else {
Eric Nelsone576bd92012-04-25 14:28:48 +0000193 flush_dcache_range((ulong)data->src,
194 (ulong)data->src+data->blocks
195 *data->blocksize);
196
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530197 if (wml_value > WML_WR_WML_MAX)
198 wml_value = WML_WR_WML_MAX_VAL;
Stefano Babicc67bee12010-02-05 15:11:27 +0100199 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
Andy Fleming50586ef2008-10-30 16:47:16 -0500200 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
201 return TIMEOUT;
202 }
Roy Zangab467c52010-02-09 18:23:33 +0800203
204 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
205 wml_value << 16);
Stefano Babicc67bee12010-02-05 15:11:27 +0100206 esdhc_write32(&regs->dsaddr, (u32)data->src);
Andy Fleming50586ef2008-10-30 16:47:16 -0500207 }
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200208#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
209 if (!(data->flags & MMC_DATA_READ)) {
210 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
211 printf("\nThe SD card is locked. "
212 "Can not write to a locked card.\n\n");
213 return TIMEOUT;
214 }
215 esdhc_write32(&regs->dsaddr, (u32)data->src);
216 } else
217 esdhc_write32(&regs->dsaddr, (u32)data->dest);
218#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
Andy Fleming50586ef2008-10-30 16:47:16 -0500219
Stefano Babicc67bee12010-02-05 15:11:27 +0100220 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
Andy Fleming50586ef2008-10-30 16:47:16 -0500221
222 /* Calculate the timeout period for data transactions */
Priyanka Jainb71ea332011-03-03 09:18:56 +0530223 /*
224 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
225 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
226 * So, Number of SD Clock cycles for 0.25sec should be minimum
227 * (SD Clock/sec * 0.25 sec) SD Clock cycles
228 * = (mmc->tran_speed * 1/4) SD Clock cycles
229 * As 1) >= 2)
230 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
231 * Taking log2 both the sides
232 * => timeout + 13 >= log2(mmc->tran_speed/4)
233 * Rounding up to next power of 2
234 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
235 * => timeout + 13 = fls(mmc->tran_speed/4)
236 */
237 timeout = fls(mmc->tran_speed/4);
Andy Fleming50586ef2008-10-30 16:47:16 -0500238 timeout -= 13;
239
240 if (timeout > 14)
241 timeout = 14;
242
243 if (timeout < 0)
244 timeout = 0;
245
Kumar Gala5103a032011-01-29 15:36:10 -0600246#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
247 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
248 timeout++;
249#endif
250
Stefano Babicc67bee12010-02-05 15:11:27 +0100251 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
Andy Fleming50586ef2008-10-30 16:47:16 -0500252
253 return 0;
254}
255
Eric Nelsone576bd92012-04-25 14:28:48 +0000256static void check_and_invalidate_dcache_range
257 (struct mmc_cmd *cmd,
258 struct mmc_data *data) {
259 unsigned start = (unsigned)data->dest ;
260 unsigned size = roundup(ARCH_DMA_MINALIGN,
261 data->blocks*data->blocksize);
262 unsigned end = start+size ;
263 invalidate_dcache_range(start, end);
264}
Andy Fleming50586ef2008-10-30 16:47:16 -0500265/*
266 * Sends a command out on the bus. Takes the mmc pointer,
267 * a command pointer, and an optional data pointer.
268 */
269static int
270esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
271{
272 uint xfertyp;
273 uint irqstat;
Stefano Babicc67bee12010-02-05 15:11:27 +0100274 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
275 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500276
Jerry Huangd621da02011-01-06 23:42:19 -0600277#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
278 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
279 return 0;
280#endif
281
Stefano Babicc67bee12010-02-05 15:11:27 +0100282 esdhc_write32(&regs->irqstat, -1);
Andy Fleming50586ef2008-10-30 16:47:16 -0500283
284 sync();
285
286 /* Wait for the bus to be idle */
Stefano Babicc67bee12010-02-05 15:11:27 +0100287 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
288 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
289 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500290
Stefano Babicc67bee12010-02-05 15:11:27 +0100291 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
292 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500293
294 /* Wait at least 8 SD clock cycles before the next command */
295 /*
296 * Note: This is way more than 8 cycles, but 1ms seems to
297 * resolve timing issues with some cards
298 */
299 udelay(1000);
300
301 /* Set up for a data transfer if we have one */
302 if (data) {
303 int err;
304
305 err = esdhc_setup_data(mmc, data);
306 if(err)
307 return err;
308 }
309
310 /* Figure out the transfer arguments */
311 xfertyp = esdhc_xfertyp(cmd, data);
312
313 /* Send the command */
Stefano Babicc67bee12010-02-05 15:11:27 +0100314 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
Jason Liu46927082011-11-25 00:18:04 +0000315#if defined(CONFIG_FSL_USDHC)
316 esdhc_write32(&regs->mixctrl,
317 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
318 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
319#else
Stefano Babicc67bee12010-02-05 15:11:27 +0100320 esdhc_write32(&regs->xfertyp, xfertyp);
Jason Liu46927082011-11-25 00:18:04 +0000321#endif
Dirk Behme7a5b8022012-03-26 03:13:05 +0000322
323 /* Mask all irqs */
324 esdhc_write32(&regs->irqsigen, 0);
325
Andy Fleming50586ef2008-10-30 16:47:16 -0500326 /* Wait for the command to complete */
Dirk Behme7a5b8022012-03-26 03:13:05 +0000327 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
Stefano Babicc67bee12010-02-05 15:11:27 +0100328 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500329
Eric Nelsone576bd92012-04-25 14:28:48 +0000330 if (data && (data->flags & MMC_DATA_READ))
331 check_and_invalidate_dcache_range(cmd, data);
332
Stefano Babicc67bee12010-02-05 15:11:27 +0100333 irqstat = esdhc_read32(&regs->irqstat);
334 esdhc_write32(&regs->irqstat, irqstat);
Andy Fleming50586ef2008-10-30 16:47:16 -0500335
Dirk Behme7a5b8022012-03-26 03:13:05 +0000336 /* Reset CMD and DATA portions on error */
337 if (irqstat & (CMD_ERR | IRQSTAT_CTOE)) {
338 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
339 SYSCTL_RSTC);
340 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
341 ;
342
343 if (data) {
344 esdhc_write32(&regs->sysctl,
345 esdhc_read32(&regs->sysctl) |
346 SYSCTL_RSTD);
347 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
348 ;
349 }
350 }
351
Andy Fleming50586ef2008-10-30 16:47:16 -0500352 if (irqstat & CMD_ERR)
353 return COMM_ERR;
354
355 if (irqstat & IRQSTAT_CTOE)
356 return TIMEOUT;
357
Dirk Behme7a5b8022012-03-26 03:13:05 +0000358 /* Workaround for ESDHC errata ENGcm03648 */
359 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
360 int timeout = 2500;
361
362 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
363 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
364 PRSSTAT_DAT0)) {
365 udelay(100);
366 timeout--;
367 }
368
369 if (timeout <= 0) {
370 printf("Timeout waiting for DAT0 to go high!\n");
371 return TIMEOUT;
372 }
373 }
374
Andy Fleming50586ef2008-10-30 16:47:16 -0500375 /* Copy the response to the response buffer */
376 if (cmd->resp_type & MMC_RSP_136) {
377 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
378
Stefano Babicc67bee12010-02-05 15:11:27 +0100379 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
380 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
381 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
382 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
Rabin Vincent998be3d2009-04-05 13:30:56 +0530383 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
384 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
385 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
386 cmd->response[3] = (cmdrsp0 << 8);
Andy Fleming50586ef2008-10-30 16:47:16 -0500387 } else
Stefano Babicc67bee12010-02-05 15:11:27 +0100388 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
Andy Fleming50586ef2008-10-30 16:47:16 -0500389
390 /* Wait until all of the blocks are transferred */
391 if (data) {
Dipen Dudhat77c14582009-10-05 15:41:58 +0530392#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
393 esdhc_pio_read_write(mmc, data);
394#else
Andy Fleming50586ef2008-10-30 16:47:16 -0500395 do {
Stefano Babicc67bee12010-02-05 15:11:27 +0100396 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleming50586ef2008-10-30 16:47:16 -0500397
Andy Fleming50586ef2008-10-30 16:47:16 -0500398 if (irqstat & IRQSTAT_DTOE)
399 return TIMEOUT;
Frans Meulenbroeks63fb5a72010-07-31 04:45:18 +0000400
401 if (irqstat & DATA_ERR)
402 return COMM_ERR;
Andy Fleming50586ef2008-10-30 16:47:16 -0500403 } while (!(irqstat & IRQSTAT_TC) &&
Stefano Babicc67bee12010-02-05 15:11:27 +0100404 (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
Dipen Dudhat77c14582009-10-05 15:41:58 +0530405#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500406 }
407
Stefano Babicc67bee12010-02-05 15:11:27 +0100408 esdhc_write32(&regs->irqstat, -1);
Andy Fleming50586ef2008-10-30 16:47:16 -0500409
410 return 0;
411}
412
413void set_sysctl(struct mmc *mmc, uint clock)
414{
415 int sdhc_clk = gd->sdhc_clk;
416 int div, pre_div;
Stefano Babicc67bee12010-02-05 15:11:27 +0100417 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
418 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500419 uint clk;
420
Stefano Babicc67bee12010-02-05 15:11:27 +0100421 if (clock < mmc->f_min)
422 clock = mmc->f_min;
423
Andy Fleming50586ef2008-10-30 16:47:16 -0500424 if (sdhc_clk / 16 > clock) {
425 for (pre_div = 2; pre_div < 256; pre_div *= 2)
426 if ((sdhc_clk / pre_div) <= (clock * 16))
427 break;
428 } else
429 pre_div = 2;
430
431 for (div = 1; div <= 16; div++)
432 if ((sdhc_clk / (div * pre_div)) <= clock)
433 break;
434
435 pre_div >>= 1;
436 div -= 1;
437
438 clk = (pre_div << 8) | (div << 4);
439
Kumar Galacc4d1222010-03-18 15:51:05 -0500440 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Stefano Babicc67bee12010-02-05 15:11:27 +0100441
442 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
Andy Fleming50586ef2008-10-30 16:47:16 -0500443
444 udelay(10000);
445
Kumar Galacc4d1222010-03-18 15:51:05 -0500446 clk = SYSCTL_PEREN | SYSCTL_CKEN;
Stefano Babicc67bee12010-02-05 15:11:27 +0100447
448 esdhc_setbits32(&regs->sysctl, clk);
Andy Fleming50586ef2008-10-30 16:47:16 -0500449}
450
451static void esdhc_set_ios(struct mmc *mmc)
452{
Stefano Babicc67bee12010-02-05 15:11:27 +0100453 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
454 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500455
456 /* Set the clock speed */
457 set_sysctl(mmc, mmc->clock);
458
459 /* Set the bus width */
Stefano Babicc67bee12010-02-05 15:11:27 +0100460 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
Andy Fleming50586ef2008-10-30 16:47:16 -0500461
462 if (mmc->bus_width == 4)
Stefano Babicc67bee12010-02-05 15:11:27 +0100463 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
Andy Fleming50586ef2008-10-30 16:47:16 -0500464 else if (mmc->bus_width == 8)
Stefano Babicc67bee12010-02-05 15:11:27 +0100465 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
466
Andy Fleming50586ef2008-10-30 16:47:16 -0500467}
468
469static int esdhc_init(struct mmc *mmc)
470{
Stefano Babicc67bee12010-02-05 15:11:27 +0100471 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
472 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500473 int timeout = 1000;
474
Stefano Babicc67bee12010-02-05 15:11:27 +0100475 /* Reset the entire host controller */
476 esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
477
478 /* Wait until the controller is available */
479 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
480 udelay(1000);
481
P.V.Suresh2c1764e2010-12-04 10:37:23 +0530482 /* Enable cache snooping */
483 if (cfg && !cfg->no_snoop)
484 esdhc_write32(&regs->scr, 0x00000040);
485
Stefano Babicc67bee12010-02-05 15:11:27 +0100486 esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
Andy Fleming50586ef2008-10-30 16:47:16 -0500487
488 /* Set the initial clock speed */
Jerry Huang4a6ee172010-11-25 17:06:07 +0000489 mmc_set_clock(mmc, 400000);
Andy Fleming50586ef2008-10-30 16:47:16 -0500490
491 /* Disable the BRR and BWR bits in IRQSTAT */
Stefano Babicc67bee12010-02-05 15:11:27 +0100492 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
Andy Fleming50586ef2008-10-30 16:47:16 -0500493
494 /* Put the PROCTL reg back to the default */
Stefano Babicc67bee12010-02-05 15:11:27 +0100495 esdhc_write32(&regs->proctl, PROCTL_INIT);
Andy Fleming50586ef2008-10-30 16:47:16 -0500496
Stefano Babicc67bee12010-02-05 15:11:27 +0100497 /* Set timout to the maximum value */
498 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
Andy Fleming50586ef2008-10-30 16:47:16 -0500499
Thierry Redingd48d2e22012-01-02 01:15:38 +0000500 return 0;
501}
Andy Fleming50586ef2008-10-30 16:47:16 -0500502
Thierry Redingd48d2e22012-01-02 01:15:38 +0000503static int esdhc_getcd(struct mmc *mmc)
504{
505 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
506 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
507 int timeout = 1000;
Stefano Babicc67bee12010-02-05 15:11:27 +0100508
Thierry Redingd48d2e22012-01-02 01:15:38 +0000509 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
510 udelay(1000);
511
512 return timeout > 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500513}
514
Jerry Huang48bb3bb2010-03-18 15:57:06 -0500515static void esdhc_reset(struct fsl_esdhc *regs)
516{
517 unsigned long timeout = 100; /* wait max 100 ms */
518
519 /* reset the controller */
520 esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
521
522 /* hardware clears the bit when it is done */
523 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
524 udelay(1000);
525 if (!timeout)
526 printf("MMC/SD: Reset never completed.\n");
527}
528
Stefano Babicc67bee12010-02-05 15:11:27 +0100529int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
Andy Fleming50586ef2008-10-30 16:47:16 -0500530{
Stefano Babicc67bee12010-02-05 15:11:27 +0100531 struct fsl_esdhc *regs;
Andy Fleming50586ef2008-10-30 16:47:16 -0500532 struct mmc *mmc;
Li Yang030955c2010-11-25 17:06:09 +0000533 u32 caps, voltage_caps;
Andy Fleming50586ef2008-10-30 16:47:16 -0500534
Stefano Babicc67bee12010-02-05 15:11:27 +0100535 if (!cfg)
536 return -1;
537
Andy Fleming50586ef2008-10-30 16:47:16 -0500538 mmc = malloc(sizeof(struct mmc));
539
Jason Liu46927082011-11-25 00:18:04 +0000540 sprintf(mmc->name, "FSL_SDHC");
Stefano Babicc67bee12010-02-05 15:11:27 +0100541 regs = (struct fsl_esdhc *)cfg->esdhc_base;
542
Jerry Huang48bb3bb2010-03-18 15:57:06 -0500543 /* First reset the eSDHC controller */
544 esdhc_reset(regs);
545
Jerry Huang975324a2012-05-17 23:57:02 +0000546 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
547 | SYSCTL_IPGEN | SYSCTL_CKEN);
548
Stefano Babicc67bee12010-02-05 15:11:27 +0100549 mmc->priv = cfg;
Andy Fleming50586ef2008-10-30 16:47:16 -0500550 mmc->send_cmd = esdhc_send_cmd;
551 mmc->set_ios = esdhc_set_ios;
552 mmc->init = esdhc_init;
Thierry Redingd48d2e22012-01-02 01:15:38 +0000553 mmc->getcd = esdhc_getcd;
Andy Fleming50586ef2008-10-30 16:47:16 -0500554
Li Yang030955c2010-11-25 17:06:09 +0000555 voltage_caps = 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500556 caps = regs->hostcapblt;
Roy Zang3b4456e2011-01-07 00:06:47 -0600557
558#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
559 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
560 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
561#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500562 if (caps & ESDHC_HOSTCAPBLT_VS18)
Li Yang030955c2010-11-25 17:06:09 +0000563 voltage_caps |= MMC_VDD_165_195;
Andy Fleming50586ef2008-10-30 16:47:16 -0500564 if (caps & ESDHC_HOSTCAPBLT_VS30)
Li Yang030955c2010-11-25 17:06:09 +0000565 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
Andy Fleming50586ef2008-10-30 16:47:16 -0500566 if (caps & ESDHC_HOSTCAPBLT_VS33)
Li Yang030955c2010-11-25 17:06:09 +0000567 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
568
569#ifdef CONFIG_SYS_SD_VOLTAGE
570 mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
571#else
572 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
573#endif
574 if ((mmc->voltages & voltage_caps) == 0) {
575 printf("voltage not supported by controller\n");
576 return -1;
577 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500578
579 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
580
581 if (caps & ESDHC_HOSTCAPBLT_HSS)
582 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
583
584 mmc->f_min = 400000;
Jerry Huang63786d22010-11-25 17:06:10 +0000585 mmc->f_max = MIN(gd->sdhc_clk, 52000000);
Andy Fleming50586ef2008-10-30 16:47:16 -0500586
Fabio Estevam1ed60d72011-05-12 09:33:27 +0000587 mmc->b_max = 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500588 mmc_register(mmc);
589
590 return 0;
591}
592
593int fsl_esdhc_mmc_init(bd_t *bis)
594{
Stefano Babicc67bee12010-02-05 15:11:27 +0100595 struct fsl_esdhc_cfg *cfg;
596
597 cfg = malloc(sizeof(struct fsl_esdhc_cfg));
598 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
599 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
600 return fsl_esdhc_initialize(bis, cfg);
Andy Fleming50586ef2008-10-30 16:47:16 -0500601}
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400602
Stefano Babicc67bee12010-02-05 15:11:27 +0100603#ifdef CONFIG_OF_LIBFDT
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400604void fdt_fixup_esdhc(void *blob, bd_t *bd)
605{
606 const char *compat = "fsl,esdhc";
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400607
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800608#ifdef CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400609 if (!hwconfig("esdhc")) {
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800610 do_fixup_by_compat(blob, compat, "status", "disabled",
611 8 + 1, 1);
612 return;
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400613 }
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800614#endif
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400615
616 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
617 gd->sdhc_clk, 1);
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800618
619 do_fixup_by_compat(blob, compat, "status", "okay",
620 4 + 1, 1);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400621}
Stefano Babicc67bee12010-02-05 15:11:27 +0100622#endif