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wdenkdb01a2e2004-04-15 23:14:49 +00001/*
2 * (C) Copyright 2003 Picture Elements, Inc.
3 * Stephen Williams <steve@icarus.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options for the JSE board
33 * (Theoretically easy to change, but the board is fixed.)
34 */
35
36#define CONFIG_JSE 1
37 /* JSE has a PPC405GPr */
38#define CONFIG_405GP 1
39 /* ... which is a 4xxx series */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_4x 1
wdenkdb01a2e2004-04-15 23:14:49 +000041 /* ... with a 33MHz OSC. connected to the SysCLK input */
42#define CONFIG_SYS_CLK_FREQ 33333333
43 /* ... with on-chip memory here (4KBytes) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
45#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
wdenkdb01a2e2004-04-15 23:14:49 +000046 /* Do not set up locked dcache as init ram. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#undef CONFIG_SYS_INIT_DCACHE_CS
wdenkdb01a2e2004-04-15 23:14:49 +000048
Wolfgang Denk2ae18242010-10-06 09:05:45 +020049#define CONFIG_SYS_TEXT_BASE 0xFFF80000
50
wdenkdb01a2e2004-04-15 23:14:49 +000051 /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
52#define CONFIG_SYSTEMACE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
54#define CONFIG_SYS_SYSTEMACE_WIDTH 8
wdenkdb01a2e2004-04-15 23:14:49 +000055#define CONFIG_DOS_PARTITION 1
56
57 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenkdb01a2e2004-04-15 23:14:49 +000059 /* ... place INIT RAM in the OCM address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
wdenkdb01a2e2004-04-15 23:14:49 +000061 /* ... give it the whole init ram */
Wolfgang Denk553f0982010-10-26 13:32:32 +020062# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
wdenkdb01a2e2004-04-15 23:14:49 +000063 /* ... Shave a bit off the end for global data */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020064# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkdb01a2e2004-04-15 23:14:49 +000065 /* ... and place the stack pointer at the top of what's left. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkdb01a2e2004-04-15 23:14:49 +000067
68 /* Enable board_pre_init function */
69#define CONFIG_BOARD_PRE_INIT 1
70#define CONFIG_BOARD_EARLY_INIT_F 1
71 /* Disable post-clk setup init function */
72#undef CONFIG_BOARD_POSTCLK_INIT
73 /* Disable call to post_init_f: late init function. */
74#undef CONFIG_POST
75 /* Enable DRAM test. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_DRAM_TEST 1
wdenkdb01a2e2004-04-15 23:14:49 +000077 /* Enable misc_init_r function. */
78#define CONFIG_MISC_INIT_R 1
79
80 /* JSE has EEPROM chips that are good for environment. */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020081#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020082#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020083#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +020084#undef CONFIG_ENV_IS_NOWHERE
wdenkdb01a2e2004-04-15 23:14:49 +000085
86 /* This is the 7bit address of the device, not including P. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
wdenkdb01a2e2004-04-15 23:14:49 +000088 /* After the device address, need one more address byte. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkdb01a2e2004-04-15 23:14:49 +000090 /* The EEPROM is 512 bytes. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_EEPROM_SIZE 512
wdenkdb01a2e2004-04-15 23:14:49 +000092 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
94#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkdb01a2e2004-04-15 23:14:49 +000095 /* Put the environment in the second half. */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020096#define CONFIG_ENV_OFFSET 0x00
97#define CONFIG_ENV_SIZE 512
wdenkdb01a2e2004-04-15 23:14:49 +000098
wdenkdb01a2e2004-04-15 23:14:49 +000099 /* The JSE connects UART1 to the console tap connector. */
Stefan Roese550650d2010-09-20 16:05:31 +0200100#define CONFIG_CONS_INDEX 2
101#define CONFIG_SYS_NS16550
102#define CONFIG_SYS_NS16550_SERIAL
103#define CONFIG_SYS_NS16550_REG_SIZE 1
104#define CONFIG_SYS_NS16550_CLK get_serial_clock()
105
wdenkdb01a2e2004-04-15 23:14:49 +0000106 /* Set console baudrate to 9600 */
107#define CONFIG_BAUDRATE 9600
108
wdenkdb01a2e2004-04-15 23:14:49 +0000109/*
110 * Configuration related to auto-boot.
111 *
112 * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
113 * before resorting to autoboot. This value can be overridden by the
114 * bootdelay environment variable.
115 *
116 * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
117 * user that an autoboot will happen.
118 *
119 * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
120 * execute to boot the JSE. This loads the uimage and initrd.img files
121 * from CompactFlash into memory, then boots them from memory.
122 *
123 * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
124 * it going on the JSE.
125 */
126#define CONFIG_BOOTDELAY 5
127#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw"
128#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
129
130
131#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkdb01a2e2004-04-15 23:14:49 +0000133
Ben Warren96e21f82008-10-27 23:50:15 -0700134#define CONFIG_PPC4xx_EMAC
wdenkdb01a2e2004-04-15 23:14:49 +0000135#define CONFIG_MII 1 /* MII PHY management */
136#define CONFIG_PHY_ADDR 1 /* PHY address */
137
wdenkdb01a2e2004-04-15 23:14:49 +0000138
Jon Loeliger348f2582007-07-08 13:46:18 -0500139/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500140 * BOOTP options
141 */
142#define CONFIG_BOOTP_BOOTFILESIZE
143#define CONFIG_BOOTP_BOOTPATH
144#define CONFIG_BOOTP_GATEWAY
145#define CONFIG_BOOTP_HOSTNAME
146
147
148/*
Jon Loeliger348f2582007-07-08 13:46:18 -0500149 * Command line configuration.
150 */
151#include <config_cmd_default.h>
152
153#define CONFIG_CMD_DHCP
154#define CONFIG_CMD_EEPROM
155#define CONFIG_CMD_ELF
156#define CONFIG_CMD_FAT
157#define CONFIG_CMD_FLASH
158#define CONFIG_CMD_IRQ
159#define CONFIG_CMD_MII
160#define CONFIG_CMD_NET
161#define CONFIG_CMD_PCI
162#define CONFIG_CMD_PING
163
wdenkdb01a2e2004-04-15 23:14:49 +0000164
165 /* watchdog disabled */
166#undef CONFIG_WATCHDOG
167 /* SPD EEPROM (sdram speed config) disabled */
wdenk24711112004-04-18 22:57:51 +0000168#undef CONFIG_SPD_EEPROM
wdenkdb01a2e2004-04-15 23:14:49 +0000169#undef SPD_EEPROM_ADDRESS
170
171/*
172 * Miscellaneous configurable options
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LONGHELP /* undef to save memory */
175#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkdb01a2e2004-04-15 23:14:49 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenkdb01a2e2004-04-15 23:14:49 +0000178
Jon Loeliger348f2582007-07-08 13:46:18 -0500179#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb01a2e2004-04-15 23:14:49 +0000181#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb01a2e2004-04-15 23:14:49 +0000183#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
185#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
186#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb01a2e2004-04-15 23:14:49 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
189#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkdb01a2e2004-04-15 23:14:49 +0000190
191/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
193 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
194 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
wdenkdb01a2e2004-04-15 23:14:49 +0000195 * The Linux BASE_BAUD define should match this configuration.
196 * baseBaud = cpuClock/(uartDivisor*16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
wdenkdb01a2e2004-04-15 23:14:49 +0000198 * set Linux BASE_BAUD to 403200.
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
201#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
202#define CONFIG_SYS_BASE_BAUD 691200
wdenkdb01a2e2004-04-15 23:14:49 +0000203
204/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkdb01a2e2004-04-15 23:14:49 +0000206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
209#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkdb01a2e2004-04-15 23:14:49 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkdb01a2e2004-04-15 23:14:49 +0000212
213#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
214#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200215#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
217#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkdb01a2e2004-04-15 23:14:49 +0000218
219
220/*-----------------------------------------------------------------------
221 * PCI stuff
222 *-----------------------------------------------------------------------
223 */
224#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
225#define PCI_HOST_FORCE 1 /* configure as pci host */
226#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
227
228#define CONFIG_PCI /* include pci support */
229#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
230#undef CONFIG_PCI_PNP /* do pci plug-and-play */
231 /* resource configuration */
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
234#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
235#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
236#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
237#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
238#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
239#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
240#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkdb01a2e2004-04-15 23:14:49 +0000241
242/*-----------------------------------------------------------------------
243 * External peripheral base address
244 *-----------------------------------------------------------------------
245 */
246#undef CONFIG_IDE_LED /* no led for ide supported */
247#undef CONFIG_IDE_RESET /* no reset for ide supported */
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
250#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
251#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
wdenkdb01a2e2004-04-15 23:14:49 +0000252
253/*-----------------------------------------------------------------------
254 * Start addresses for the final memory configuration
255 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkdb01a2e2004-04-15 23:14:49 +0000257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SDRAM_BASE 0x00000000
259#define CONFIG_SYS_FLASH_BASE 0xFFF80000
260#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
261#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
262#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkdb01a2e2004-04-15 23:14:49 +0000263
264/*
265 * For booting Linux, the board info and command line data
266 * have to be in the first 8 MB of memory, since this is
267 * the maximum mapped by the Linux kernel during initialization.
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb01a2e2004-04-15 23:14:49 +0000270
271/*-----------------------------------------------------------------------
272 * FLASH organization
273 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
275#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkdb01a2e2004-04-15 23:14:49 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
278#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkdb01a2e2004-04-15 23:14:49 +0000279
wdenkdb01a2e2004-04-15 23:14:49 +0000280/*
281 * Init Memory Controller:
282 *
283 * BR0/1 and OR0/1 (FLASH)
284 */
285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
wdenkdb01a2e2004-04-15 23:14:49 +0000287#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
288
289
290/* Configuration Port location */
291#define CONFIG_PORT_ADDR 0xF0000500
292
Jon Loeliger348f2582007-07-08 13:46:18 -0500293#if defined(CONFIG_CMD_KGDB)
wdenkdb01a2e2004-04-15 23:14:49 +0000294#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
295#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
296#endif
297#endif /* __CONFIG_H */