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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05302/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on da830evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05309 */
10
11#include <common.h>
Adam Ford8e51c0f2018-06-10 22:25:57 -050012#include <dm.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060013#include <env.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053014#include <i2c.h>
Simon Glass691d7192020-05-10 11:40:02 -060015#include <init.h>
Ben Gardiner3d248d32010-10-14 17:26:29 -040016#include <net.h>
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +000017#include <spi.h>
18#include <spi_flash.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053019#include <asm/arch/hardware.h>
Simon Glass401d1c42020-10-30 21:38:53 -060020#include <asm/global_data.h>
Khoronzhuk, Ivan3e01ed02014-06-07 04:22:52 +030021#include <asm/ti-common/davinci_nand.h>
Ben Gardiner3d248d32010-10-14 17:26:29 -040022#include <asm/arch/emac_defs.h>
Christian Riesch52b0f872011-11-28 23:46:18 +000023#include <asm/arch/pinmux_defs.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053024#include <asm/io.h>
Sughosh Ganud7f9b502010-11-28 20:21:27 -050025#include <asm/arch/davinci_misc.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090026#include <linux/errno.h>
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -040027#include <hwconfig.h>
Simon Glassc62db352017-05-31 19:47:48 -060028#include <asm/mach-types.h>
Adam Ford8e51c0f2018-06-10 22:25:57 -050029#include <asm/gpio.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053030
Masahiro Yamada1d2c0502017-01-10 13:32:07 +090031#ifdef CONFIG_MMC_DAVINCI
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +000032#include <mmc.h>
33#include <asm/arch/sdmmc_defs.h>
34#endif
35
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053036DECLARE_GLOBAL_DATA_PTR;
37
Ben Gardiner3d248d32010-10-14 17:26:29 -040038#ifdef CONFIG_DRIVER_TI_EMAC
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -050039#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
40#define HAS_RMII 1
41#else
42#define HAS_RMII 0
43#endif
44#endif /* CONFIG_DRIVER_TI_EMAC */
45
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +000046#define CFG_MAC_ADDR_SPI_BUS 0
47#define CFG_MAC_ADDR_SPI_CS 0
48#define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
49#define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
50
51#define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
52
53#ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
54static int get_mac_addr(u8 *addr)
55{
56 struct spi_flash *flash;
57 int ret;
58
59 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
60 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
61 if (!flash) {
62 printf("Error - unable to probe SPI flash.\n");
63 return -1;
64 }
65
Adam Ford4fde31e2019-05-29 09:36:58 -050066 ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +000067 if (ret) {
68 printf("Error - unable to read MAC address from SPI flash.\n");
69 return -1;
70 }
71
72 return ret;
73}
74#endif
75
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -040076void dsp_lpsc_on(unsigned domain, unsigned int id)
77{
78 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
79 struct davinci_psc_regs *psc_regs;
80
81 psc_regs = davinci_psc0_regs;
82 mdstat = &psc_regs->psc0.mdstat[id];
83 mdctl = &psc_regs->psc0.mdctl[id];
84 ptstat = &psc_regs->ptstat;
85 ptcmd = &psc_regs->ptcmd;
86
87 while (*ptstat & (0x1 << domain))
88 ;
89
90 if ((*mdstat & 0x1f) == 0x03)
91 return; /* Already on and enabled */
92
93 *mdctl |= 0x03;
94
95 *ptcmd = 0x1 << domain;
96
97 while (*ptstat & (0x1 << domain))
98 ;
99 while ((*mdstat & 0x1f) != 0x03)
100 ; /* Probably an overkill... */
101}
102
103static void dspwake(void)
104{
105 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
106 u32 val;
107
108 /* if the device is ARM only, return */
109 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
110 return;
111
112 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
113 return;
114
115 *resetvect++ = 0x1E000; /* DSP Idle */
116 /* clear out the next 10 words as NOP */
117 memset(resetvect, 0, sizeof(unsigned) *10);
118
119 /* setup the DSP reset vector */
120 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
121
122 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
123 val = readl(PSC0_MDCTL + (15 * 4));
124 val |= 0x100;
125 writel(val, (PSC0_MDCTL + (15 * 4)));
126}
127
128int misc_init_r(void)
129{
130 dspwake();
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +0000131
Tom Rini20815ec2021-08-17 17:59:37 -0400132#if defined(CONFIG_MAC_ADDR_IN_SPIFLASH)
133 uchar env_enetaddr[6], buff[6];
134 int enetaddr_found, spi_mac_read;
Hadli, Manjunath206a1032012-02-09 20:22:25 +0000135
Simon Glass35affd72017-08-03 12:22:14 -0600136 enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
Hadli, Manjunath206a1032012-02-09 20:22:25 +0000137
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +0000138 spi_mac_read = get_mac_addr(buff);
Adam Forda4670f82017-09-17 20:43:46 -0500139 buff[0] = 0;
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +0000140
141 /*
142 * MAC address not present in the environment
143 * try and read the MAC address from SPI flash
144 * and set it.
145 */
146 if (!enetaddr_found) {
147 if (!spi_mac_read) {
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500148 if (is_valid_ethaddr(buff)) {
Simon Glassfd1e9592017-08-03 12:22:11 -0600149 if (eth_env_set_enetaddr("ethaddr", buff)) {
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +0000150 printf("Warning: Failed to "
151 "set MAC address from SPI flash\n");
152 }
153 } else {
154 printf("Warning: Invalid "
155 "MAC address read from SPI flash\n");
156 }
157 }
158 } else {
159 /*
160 * MAC address present in environment compare it with
161 * the MAC address in SPI flash and warn on mismatch
162 */
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500163 if (!spi_mac_read && is_valid_ethaddr(buff) &&
164 memcmp(env_enetaddr, buff, 6))
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +0000165 printf("Warning: MAC address in SPI flash don't match "
166 "with the MAC address in the environment\n");
Andre Przywarabb72b942016-11-16 00:50:12 +0000167 printf("Default using MAC address from environment\n");
Hadli, Manjunath38fed6e2012-02-09 20:22:24 +0000168 }
Hadli, Manjunath206a1032012-02-09 20:22:25 +0000169#endif
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -0400170 return 0;
171}
172
Christian Riesch52b0f872011-11-28 23:46:18 +0000173static const struct pinmux_config gpio_pins[] = {
Adam Ford7bb33e42020-06-29 18:49:41 -0500174#ifdef CONFIG_MTD_NOR_FLASH
Christian Riesch52b0f872011-11-28 23:46:18 +0000175 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
176 { pinmux(0), 8, 4 }, /* GP0[11] */
177#endif
Masahiro Yamada1d2c0502017-01-10 13:32:07 +0900178#ifdef CONFIG_MMC_DAVINCI
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000179 /* GP0[11] is required for SD to work on Rev 3 EVMs */
180 { pinmux(0), 8, 4 }, /* GP0[11] */
181#endif
Christian Riesch52b0f872011-11-28 23:46:18 +0000182};
183
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000184const struct pinmux_resource pinmuxes[] = {
Christian Riesch591d8012011-11-28 23:46:16 +0000185#ifdef CONFIG_DRIVER_TI_EMAC
Christian Riesch52b0f872011-11-28 23:46:18 +0000186 PINMUX_ITEM(emac_pins_mdio),
187#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
188 PINMUX_ITEM(emac_pins_rmii),
189#else
190 PINMUX_ITEM(emac_pins_mii),
Adam Fordb9ad74d2019-07-31 09:17:31 -0500191#endif
192#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530193#ifdef CONFIG_SPI_FLASH
Christian Riesch52b0f872011-11-28 23:46:18 +0000194 PINMUX_ITEM(spi1_pins_base),
195 PINMUX_ITEM(spi1_pins_scs0),
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530196#endif
Christian Riesch52b0f872011-11-28 23:46:18 +0000197 PINMUX_ITEM(uart2_pins_txrx),
198 PINMUX_ITEM(uart2_pins_rtscts),
199 PINMUX_ITEM(i2c0_pins),
Ben Gardiner756d1fe2010-10-14 17:26:19 -0400200#ifdef CONFIG_NAND_DAVINCI
Christian Riesch52b0f872011-11-28 23:46:18 +0000201 PINMUX_ITEM(emifa_pins_cs3),
202 PINMUX_ITEM(emifa_pins_cs4),
203 PINMUX_ITEM(emifa_pins_nand),
Adam Ford7bb33e42020-06-29 18:49:41 -0500204#elif defined(CONFIG_MTD_NOR_FLASH)
Christian Riesch52b0f872011-11-28 23:46:18 +0000205 PINMUX_ITEM(emifa_pins_cs2),
206 PINMUX_ITEM(emifa_pins_nor),
Ben Gardiner756d1fe2010-10-14 17:26:19 -0400207#endif
Christian Riesch52b0f872011-11-28 23:46:18 +0000208 PINMUX_ITEM(gpio_pins),
Masahiro Yamada1d2c0502017-01-10 13:32:07 +0900209#ifdef CONFIG_MMC_DAVINCI
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000210 PINMUX_ITEM(mmc0_pins),
211#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530212};
213
Christian Riesch3d2c8e62011-12-09 09:47:37 +0000214const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
215
Sughosh Ganu6b873dc2012-02-02 00:44:41 +0000216const struct lpsc_resource lpsc[] = {
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530217 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
218 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
219 { DAVINCI_LPSC_EMAC }, /* image download */
220 { DAVINCI_LPSC_UART2 }, /* console */
221 { DAVINCI_LPSC_GPIO },
Masahiro Yamada1d2c0502017-01-10 13:32:07 +0900222#ifdef CONFIG_MMC_DAVINCI
Lad, Prabhakarecc98ec2012-06-24 21:35:15 +0000223 { DAVINCI_LPSC_MMC_SD },
224#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530225};
226
Sughosh Ganu6b873dc2012-02-02 00:44:41 +0000227const int lpsc_size = ARRAY_SIZE(lpsc);
228
Tom Rini6e7df1d2023-01-10 11:19:45 -0500229#ifndef CFG_DA850_EVM_MAX_CPU_CLK
230#define CFG_DA850_EVM_MAX_CPU_CLK 300000000
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500231#endif
232
Manjunath Hadli754f8cb2011-10-10 21:06:38 +0000233#define REV_AM18X_EVM 0x100
234
Tom Rini97744622021-08-30 09:16:30 -0400235#ifdef CONFIG_REVISION_TAG
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500236/*
237 * get_board_rev() - setup to pass kernel board revision information
238 * Returns:
239 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
240 * 0000b - 300 MHz
241 * 0001b - 372 MHz
242 * 0010b - 408 MHz
243 * 0011b - 456 MHz
244 */
245u32 get_board_rev(void)
246{
247 char *s;
Tom Rini6e7df1d2023-01-10 11:19:45 -0500248 u32 maxcpuclk = CFG_DA850_EVM_MAX_CPU_CLK;
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500249 u32 rev = 0;
250
Simon Glass00caae62017-08-03 12:22:12 -0600251 s = env_get("maxcpuclk");
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500252 if (s)
Simon Glass0b1284e2021-07-24 09:03:30 -0600253 maxcpuclk = dectoul(s, NULL);
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500254
255 if (maxcpuclk >= 456000000)
256 rev = 3;
257 else if (maxcpuclk >= 408000000)
258 rev = 2;
259 else if (maxcpuclk >= 372000000)
260 rev = 1;
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500261 return rev;
262}
Tom Rini97744622021-08-30 09:16:30 -0400263#endif
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500264
Christian Rieschae5c77d2011-10-13 00:52:29 +0000265int board_early_init_f(void)
266{
267 /*
268 * Power on required peripherals
269 * ARM does not have access by default to PSC0 and PSC1
270 * assuming here that the DSP bootloader has set the IOPU
271 * such that PSC access is available to ARM
272 */
273 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
274 return 1;
275
276 return 0;
277}
278
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530279int board_init(void)
280{
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530281 irq_init();
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530282
Ben Gardinera3f88292010-10-14 17:26:22 -0400283#ifdef CONFIG_NAND_DAVINCI
284 /*
285 * NAND CS setup - cycle counts based on da850evm NAND timings in the
286 * Linux kernel @ 25MHz EMIFA
287 */
Lad, Prabhakarde94b802012-06-24 21:35:21 +0000288 writel((DAVINCI_ABCR_WSETUP(2) |
289 DAVINCI_ABCR_WSTROBE(2) |
290 DAVINCI_ABCR_WHOLD(1) |
291 DAVINCI_ABCR_RSETUP(1) |
292 DAVINCI_ABCR_RSTROBE(4) |
Ben Gardinera3f88292010-10-14 17:26:22 -0400293 DAVINCI_ABCR_RHOLD(0) |
Ben Gardiner24a514c2011-04-20 16:25:06 -0400294 DAVINCI_ABCR_TA(1) |
Ben Gardinera3f88292010-10-14 17:26:22 -0400295 DAVINCI_ABCR_ASIZE_8BIT),
296 &davinci_emif_regs->ab2cr); /* CS3 */
297#endif
298
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530299 /* arch number of the board */
300 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
301
302 /* address of boot parameters */
303 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
304
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530305 /* setup the SUSPSRC for ARM to control emulation suspend */
306 writel(readl(&davinci_syscfg_regs->suspsrc) &
307 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
308 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
309 DAVINCI_SYSCFG_SUSPSRC_UART2),
310 &davinci_syscfg_regs->suspsrc);
311
Adam Ford7bb33e42020-06-29 18:49:41 -0500312#ifdef CONFIG_MTD_NOR_FLASH
Nagabhushana Netagunte0f3d6b02011-09-03 22:21:04 -0400313 /* Set the GPIO direction as output */
Christian Riesch3864cb22013-06-14 14:22:36 +0200314 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
Nagabhushana Netagunte0f3d6b02011-09-03 22:21:04 -0400315
316 /* Set the output as low */
Christian Riesch3864cb22013-06-14 14:22:36 +0200317 writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
Nagabhushana Netagunte0f3d6b02011-09-03 22:21:04 -0400318#endif
319
Masahiro Yamada1d2c0502017-01-10 13:32:07 +0900320#ifdef CONFIG_MMC_DAVINCI
Rajashekhara, Sudhakar6652c622012-06-24 21:35:16 +0000321 /* Set the GPIO direction as output */
322 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
323
324 /* Set the output as high */
Christian Riesch3864cb22013-06-14 14:22:36 +0200325 writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
Rajashekhara, Sudhakar6652c622012-06-24 21:35:16 +0000326#endif
327
Ben Gardiner3d248d32010-10-14 17:26:29 -0400328#ifdef CONFIG_DRIVER_TI_EMAC
Stefano Babic6d1c6492010-11-30 11:32:10 -0500329 davinci_emac_mii_mode_sel(HAS_RMII);
Ben Gardiner3d248d32010-10-14 17:26:29 -0400330#endif /* CONFIG_DRIVER_TI_EMAC */
331
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530332 return 0;
333}
Ben Gardiner3d248d32010-10-14 17:26:29 -0400334
335#ifdef CONFIG_DRIVER_TI_EMAC
336
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500337#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
338/**
339 * rmii_hw_init
340 *
341 * DA850/OMAP-L138 EVM can interface to a daughter card for
342 * additional features. This card has an I2C GPIO Expander TCA6416
343 * to select the required functions like camera, RMII Ethernet,
344 * character LCD, video.
345 *
346 * Initialization of the expander involves configuring the
347 * polarity and direction of the ports. P07-P05 are used here.
348 * These ports are connected to a Mux chip which enables only one
349 * functionality at a time.
350 *
351 * For RMII phy to respond, the MII MDIO clock has to be disabled
352 * since both the PHY devices have address as zero. The MII MDIO
353 * clock is controlled via GPIO2[6].
354 *
355 * This code is valid for Beta version of the hardware
356 */
357int rmii_hw_init(void)
358{
359 const struct pinmux_config gpio_pins[] = {
360 { pinmux(6), 8, 1 }
361 };
362 u_int8_t buf[2];
363 unsigned int temp;
364 int ret;
365
366 /* PinMux for GPIO */
367 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
368 return 1;
369
370 /* I2C Exapnder configuration */
371 /* Set polarity to non-inverted */
372 buf[0] = 0x0;
373 buf[1] = 0x0;
Tom Rini65cc0e22022-11-16 13:10:41 -0500374 ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500375 if (ret) {
376 printf("\nExpander @ 0x%02x write FAILED!!!\n",
Tom Rini65cc0e22022-11-16 13:10:41 -0500377 CFG_SYS_I2C_EXPANDER_ADDR);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500378 return ret;
379 }
380
381 /* Configure P07-P05 as outputs */
382 buf[0] = 0x1f;
383 buf[1] = 0xff;
Tom Rini65cc0e22022-11-16 13:10:41 -0500384 ret = i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500385 if (ret) {
386 printf("\nExpander @ 0x%02x write FAILED!!!\n",
Tom Rini65cc0e22022-11-16 13:10:41 -0500387 CFG_SYS_I2C_EXPANDER_ADDR);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500388 }
389
390 /* For Ethernet RMII selection
391 * P07(SelA)=0
392 * P06(SelB)=1
393 * P05(SelC)=1
394 */
Tom Rini65cc0e22022-11-16 13:10:41 -0500395 if (i2c_read(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500396 printf("\nExpander @ 0x%02x read FAILED!!!\n",
Tom Rini65cc0e22022-11-16 13:10:41 -0500397 CFG_SYS_I2C_EXPANDER_ADDR);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500398 }
399
400 buf[0] &= 0x1f;
401 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
Tom Rini65cc0e22022-11-16 13:10:41 -0500402 if (i2c_write(CFG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500403 printf("\nExpander @ 0x%02x write FAILED!!!\n",
Tom Rini65cc0e22022-11-16 13:10:41 -0500404 CFG_SYS_I2C_EXPANDER_ADDR);
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500405 }
406
407 /* Set the output as high */
408 temp = REG(GPIO_BANK2_REG_SET_ADDR);
409 temp |= (0x01 << 6);
410 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
411
412 /* Set the GPIO direction as output */
413 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
414 temp &= ~(0x01 << 6);
415 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
416
417 return 0;
418}
419#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
420
Ben Gardiner3d248d32010-10-14 17:26:29 -0400421/*
422 * Initializes on-board ethernet controllers.
423 */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900424int board_eth_init(struct bd_info *bis)
Ben Gardiner3d248d32010-10-14 17:26:29 -0400425{
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500426#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
427 /* Select RMII fucntion through the expander */
428 if (rmii_hw_init())
429 printf("RMII hardware init failed!!!\n");
430#endif
Ben Gardiner3d248d32010-10-14 17:26:29 -0400431 return 0;
432}
433#endif /* CONFIG_DRIVER_TI_EMAC */