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Peng Fan3f2b4d72021-08-07 16:01:13 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020 NXP
4 */
5
6#ifndef __IMX8ULP_EVK_H
7#define __IMX8ULP_EVK_H
8
9#include <linux/sizes.h>
10#include <asm/arch/imx-regs.h>
11
Tom Rini65cc0e22022-11-16 13:10:41 -050012#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
Peng Fan3f2b4d72021-08-07 16:01:13 +080013
14#ifdef CONFIG_SPL_BUILD
Tom Rinidd5b58c2022-12-04 10:04:49 -050015#define CFG_MALLOC_F_ADDR 0x22040000
Peng Fan3f2b4d72021-08-07 16:01:13 +080016
Peng Fan3f2b4d72021-08-07 16:01:13 +080017
18#endif
19
Peng Fan3f2b4d72021-08-07 16:01:13 +080020/* ENET Config */
21#if defined(CONFIG_FEC_MXC)
Peng Fan3f2b4d72021-08-07 16:01:13 +080022#define PHY_ANEG_TIMEOUT 20000
23
Tom Rinifa760c32022-12-04 10:03:53 -050024#define CFG_FEC_MXC_PHYADDR 1
Peng Fan3f2b4d72021-08-07 16:01:13 +080025#endif
26
27#ifdef CONFIG_DISTRO_DEFAULTS
28#define BOOT_TARGET_DEVICES(func) \
29 func(MMC, mmc, 0)
30
31#include <config_distro_bootcmd.h>
32#else
33#define BOOTENV
34#endif
35
36/* Initial environment variables */
Tom Rini0613c362022-12-04 10:03:50 -050037#define CFG_EXTRA_ENV_SETTINGS \
Peng Fan3f2b4d72021-08-07 16:01:13 +080038 BOOTENV \
Tom Rini72d81362021-08-23 10:25:30 -040039 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
40 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Peng Fan3f2b4d72021-08-07 16:01:13 +080041 "image=Image\0" \
42 "console=ttyLP1,115200 earlycon\0" \
43 "fdt_addr_r=0x83000000\0" \
44 "boot_fit=no\0" \
45 "fdtfile=imx8ulp-evk.dtb\0" \
46 "initrd_addr=0x83800000\0" \
47 "bootm_size=0x10000000\0" \
Tom Rinide35b8f2021-12-11 14:55:52 -050048 "mmcpart=1\0" \
Peng Fanadfaa422022-04-15 12:23:41 +080049 "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
Peng Fan3f2b4d72021-08-07 16:01:13 +080050
51/* Link Definitions */
Peng Fan3f2b4d72021-08-07 16:01:13 +080052
Tom Rini65cc0e22022-11-16 13:10:41 -050053#define CFG_SYS_INIT_RAM_ADDR 0x80000000
54#define CFG_SYS_INIT_RAM_SIZE 0x80000
Peng Fan3f2b4d72021-08-07 16:01:13 +080055
Peng Fan3f2b4d72021-08-07 16:01:13 +080056
Tom Riniaa6e94d2022-11-16 13:10:37 -050057#define CFG_SYS_SDRAM_BASE 0x80000000
Peng Fan3f2b4d72021-08-07 16:01:13 +080058#define PHYS_SDRAM 0x80000000
59#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
60
Peng Fan3f2b4d72021-08-07 16:01:13 +080061/* Using ULP WDOG for reset */
62#define WDOG_BASE_ADDR WDG3_RBASE
63#endif