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Stefan Roese7644f162005-09-22 09:16:57 +02001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese7644f162005-09-22 09:16:57 +02006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Stefan Roese7644f162005-09-22 09:16:57 +020021
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
Matthias Fuchs37ea0092015-01-12 22:47:32 +010023#define CONFIG_DISPLAY_BOARDINFO
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024
Stefan Roese7644f162005-09-22 09:16:57 +020025#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
26
27#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
28
29#define CONFIG_BAUDRATE 9600
Stefan Roese7644f162005-09-22 09:16:57 +020030
31#undef CONFIG_BOOTARGS
32#undef CONFIG_BOOTCOMMAND
33
34#define CONFIG_PREBOOT /* enable preboot variable */
35
36#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese7644f162005-09-22 09:16:57 +020038
39#define CONFIG_MII 1 /* MII PHY management */
40#define CONFIG_PHY_ADDR 0 /* PHY address */
41
Jon Loeliger49cf7e82007-07-05 19:52:35 -050042/*
Jon Loeliger11799432007-07-10 09:02:57 -050043 * BOOTP options
44 */
45#define CONFIG_BOOTP_BOOTFILESIZE
46#define CONFIG_BOOTP_BOOTPATH
47#define CONFIG_BOOTP_GATEWAY
48#define CONFIG_BOOTP_HOSTNAME
49
Jon Loeliger11799432007-07-10 09:02:57 -050050/*
Jon Loeliger49cf7e82007-07-05 19:52:35 -050051 * Command line configuration.
52 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050053#define CONFIG_CMD_PCI
54#define CONFIG_CMD_IRQ
Jon Loeliger49cf7e82007-07-05 19:52:35 -050055#define CONFIG_CMD_BSP
56#define CONFIG_CMD_EEPROM
57
Stefan Roese7644f162005-09-22 09:16:57 +020058#undef CONFIG_WATCHDOG /* watchdog disabled */
59
60#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
61
62/*
63 * Miscellaneous configurable options
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_LONGHELP /* undef to save memory */
Stefan Roese7644f162005-09-22 09:16:57 +020066
Jon Loeliger49cf7e82007-07-05 19:52:35 -050067#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese7644f162005-09-22 09:16:57 +020069#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese7644f162005-09-22 09:16:57 +020071#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
73#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
74#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese7644f162005-09-22 09:16:57 +020075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
Stefan Roese7644f162005-09-22 09:16:57 +020077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
Stefan Roese7644f162005-09-22 09:16:57 +020079
80#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
83#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese7644f162005-09-22 09:16:57 +020084
Stefan Roese550650d2010-09-20 16:05:31 +020085#define CONFIG_CONS_INDEX 2 /* Use UART1 */
Stefan Roese550650d2010-09-20 16:05:31 +020086#define CONFIG_SYS_NS16550_SERIAL
87#define CONFIG_SYS_NS16550_REG_SIZE 1
88#define CONFIG_SYS_NS16550_CLK get_serial_clock()
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese7644f162005-09-22 09:16:57 +020092
93/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roese7644f162005-09-22 09:16:57 +020095 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
96 57600, 115200, 230400, 460800, 921600 }
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
99#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese7644f162005-09-22 09:16:57 +0200100
Stefan Roese7644f162005-09-22 09:16:57 +0200101#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
Stefan Roese7644f162005-09-22 09:16:57 +0200104
105/*-----------------------------------------------------------------------
106 * PCI stuff
107 *-----------------------------------------------------------------------
108 */
109#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
110#define PCI_HOST_FORCE 1 /* configure as pci host */
111#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
112
113#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000114#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese7644f162005-09-22 09:16:57 +0200115#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
116#define CONFIG_PCI_PNP /* do pci plug-and-play */
117 /* resource configuration */
118
119#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
120
121#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
122
123#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
126#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
127#define CONFIG_SYS_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
Stefan Roese2076d0a2006-01-18 20:03:15 +0100128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
130#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
131#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
132#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
133#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
134#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
Stefan Roese7644f162005-09-22 09:16:57 +0200135
136/*-----------------------------------------------------------------------
137 * Start addresses for the final memory configuration
138 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roese7644f162005-09-22 09:16:57 +0200140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_SDRAM_BASE 0x00000000
142#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
143#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
144#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
145#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Stefan Roese7644f162005-09-22 09:16:57 +0200146
147/*
148 * For booting Linux, the board info and command line data
149 * have to be in the first 8 MB of memory, since this is
150 * the maximum mapped by the Linux kernel during initialization.
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese7644f162005-09-22 09:16:57 +0200153/*-----------------------------------------------------------------------
154 * FLASH organization
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
157#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Stefan Roese7644f162005-09-22 09:16:57 +0200158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
160#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese7644f162005-09-22 09:16:57 +0200161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
163#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
164#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Stefan Roese7644f162005-09-22 09:16:57 +0200165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
167#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
168#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
Stefan Roese7644f162005-09-22 09:16:57 +0200169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese7644f162005-09-22 09:16:57 +0200171
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200172#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200173#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
174#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
Stefan Roese7644f162005-09-22 09:16:57 +0200175
176/*-----------------------------------------------------------------------
177 * I2C EEPROM (CAT24WC16) for environment
178 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000179#define CONFIG_SYS_I2C
180#define CONFIG_SYS_I2C_PPC4XX
181#define CONFIG_SYS_I2C_PPC4XX_CH0
182#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
183#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Stefan Roese7644f162005-09-22 09:16:57 +0200184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
186#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese7644f162005-09-22 09:16:57 +0200187/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
189#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
Stefan Roese7644f162005-09-22 09:16:57 +0200190 /* 16 byte page write mode using*/
191 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roese7644f162005-09-22 09:16:57 +0200193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roese7644f162005-09-22 09:16:57 +0200195
Stefan Roese7644f162005-09-22 09:16:57 +0200196/*
197 * Init Memory Controller:
198 *
199 * BR0/1 and OR0/1 (FLASH)
200 */
201#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
202#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
203
204/*-----------------------------------------------------------------------
205 * External Bus Controller (EBC) Setup
206 */
207
208/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_EBC_PB0AP 0x92015480
210#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
Stefan Roese7644f162005-09-22 09:16:57 +0200211
212/* Memory Bank 2 (PB0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
214#define CONFIG_SYS_EBC_PB2CR 0xEF018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese7644f162005-09-22 09:16:57 +0200215
216/* Memory Bank 3 (PB1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
218#define CONFIG_SYS_EBC_PB3CR 0xEF118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese7644f162005-09-22 09:16:57 +0200219
220/*-----------------------------------------------------------------------
221 * Definitions for initial stack pointer and data area (in data cache)
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
Stefan Roese7644f162005-09-22 09:16:57 +0200224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200226#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200227#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese7644f162005-09-22 09:16:57 +0200229
230/*-----------------------------------------------------------------------
231 * GPIO definitions
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
234#define CONFIG_SYS_SELF_RST (0x80000000 >> 14) /* GPIO14 */
235#define CONFIG_SYS_PB_LED (0x80000000 >> 16) /* GPIO16 */
236#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
Stefan Roese7644f162005-09-22 09:16:57 +0200237
Stefan Roese7644f162005-09-22 09:16:57 +0200238#endif /* __CONFIG_H */