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wdenkd126bfb2003-04-10 11:18:18 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkd126bfb2003-04-10 11:18:18 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkd126bfb2003-04-10 11:18:18 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1
21#define CONFIG_MPC860T 1
22#define CONFIG_MPC862 1
Wolfgang Denk23c5d252014-10-24 15:31:26 +020023#define CONFIG_DISPLAY_BOARDINFO
wdenkd126bfb2003-04-10 11:18:18 +000024
25#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0x40000000
28
wdenkd126bfb2003-04-10 11:18:18 +000029#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020030#define CONFIG_SYS_SMC_RXBUFLEN 128
31#define CONFIG_SYS_MAXIDLE 10
wdenkd126bfb2003-04-10 11:18:18 +000032#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
33
wdenkae3af052003-08-07 22:18:11 +000034#define CONFIG_BOOTCOUNT_LIMIT
wdenkd126bfb2003-04-10 11:18:18 +000035
wdenkd126bfb2003-04-10 11:18:18 +000036
37#define CONFIG_BOARD_TYPES 1 /* support board types */
38
39#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010040 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd126bfb2003-04-10 11:18:18 +000041 "echo"
42
43#undef CONFIG_BOOTARGS
44
45#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000046 "netdev=eth0\0" \
wdenkd126bfb2003-04-10 11:18:18 +000047 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010048 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd126bfb2003-04-10 11:18:18 +000049 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "addip=setenv bootargs ${bootargs} " \
51 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
52 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd126bfb2003-04-10 11:18:18 +000053 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010054 "bootm ${kernel_addr}\0" \
wdenkd126bfb2003-04-10 11:18:18 +000055 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
57 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd126bfb2003-04-10 11:18:18 +000058 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020059 "hostname=TQM862L\0" \
60 "bootfile=TQM862L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020061 "fdt_addr=40040000\0" \
62 "kernel_addr=40060000\0" \
63 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020064 "u-boot=TQM862L/u-image.bin\0" \
65 "load=tftp 200000 ${u-boot}\0" \
66 "update=prot off 40000000 +${filesize};" \
67 "era 40000000 +${filesize};" \
68 "cp.b 200000 40000000 ${filesize};" \
69 "sete filesize;save\0" \
wdenkd126bfb2003-04-10 11:18:18 +000070 ""
71#define CONFIG_BOOTCOMMAND "run flash_self"
72
73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkd126bfb2003-04-10 11:18:18 +000075
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
78#define CONFIG_STATUS_LED 1 /* Status LED enabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
Jon Loeliger37d4bb72007-07-09 21:38:02 -050082/*
83 * BOOTP options
84 */
85#define CONFIG_BOOTP_SUBNETMASK
86#define CONFIG_BOOTP_GATEWAY
87#define CONFIG_BOOTP_HOSTNAME
88#define CONFIG_BOOTP_BOOTPATH
89#define CONFIG_BOOTP_BOOTFILESIZE
90
wdenkd126bfb2003-04-10 11:18:18 +000091#define CONFIG_MAC_PARTITION
92#define CONFIG_DOS_PARTITION
93
94#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95
Jon Loeliger26946902007-07-04 22:30:50 -050096/*
97 * Command line configuration.
98 */
Jon Loeliger26946902007-07-04 22:30:50 -050099#define CONFIG_CMD_DATE
Jon Loeliger26946902007-07-04 22:30:50 -0500100#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200101#define CONFIG_CMD_JFFS2
wdenkd126bfb2003-04-10 11:18:18 +0000102
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200103#define CONFIG_NETCONSOLE
104
wdenkd126bfb2003-04-10 11:18:18 +0000105/*
106 * Miscellaneous configurable options
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkd126bfb2003-04-10 11:18:18 +0000109
Wolfgang Denk2751a952006-10-28 02:29:14 +0200110#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenkd126bfb2003-04-10 11:18:18 +0000111
Jon Loeliger26946902007-07-04 22:30:50 -0500112#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd126bfb2003-04-10 11:18:18 +0000114#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd126bfb2003-04-10 11:18:18 +0000116#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
118#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
119#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkd126bfb2003-04-10 11:18:18 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
122#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkd126bfb2003-04-10 11:18:18 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkd126bfb2003-04-10 11:18:18 +0000125
wdenkd126bfb2003-04-10 11:18:18 +0000126/*
127 * Low Level Configuration Settings
128 * (address mappings, register initial values, etc.)
129 * You should know what you are doing if you make changes here.
130 */
131/*-----------------------------------------------------------------------
132 * Internal Memory Mapped Register
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_IMMR 0xFFF00000
wdenkd126bfb2003-04-10 11:18:18 +0000135
136/*-----------------------------------------------------------------------
137 * Definitions for initial stack pointer and data area (in DPRAM)
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200140#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200141#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkd126bfb2003-04-10 11:18:18 +0000143
144/*-----------------------------------------------------------------------
145 * Start addresses for the final memory configuration
146 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkd126bfb2003-04-10 11:18:18 +0000148 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_SDRAM_BASE 0x00000000
150#define CONFIG_SYS_FLASH_BASE 0x40000000
151#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
152#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
153#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkd126bfb2003-04-10 11:18:18 +0000154
155/*
156 * For booting Linux, the board info and command line data
157 * have to be in the first 8 MB of memory, since this is
158 * the maximum mapped by the Linux kernel during initialization.
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd126bfb2003-04-10 11:18:18 +0000161
162/*-----------------------------------------------------------------------
163 * FLASH organization
164 */
wdenkd126bfb2003-04-10 11:18:18 +0000165
Martin Krausee318d9e2007-09-27 11:10:08 +0200166/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200168#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
170#define CONFIG_SYS_FLASH_EMPTY_INFO
171#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
172#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
173#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkd126bfb2003-04-10 11:18:18 +0000174
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200175#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200176#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
177#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkd126bfb2003-04-10 11:18:18 +0000178
179/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
181#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkd126bfb2003-04-10 11:18:18 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200184
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200185#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
186
wdenkd126bfb2003-04-10 11:18:18 +0000187/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200188 * Dynamic MTD partition support
189 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100190#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200191#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
192#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200193#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
194
195#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
196 "128k(dtb)," \
197 "1664k(kernel)," \
198 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200199 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200200
201/*-----------------------------------------------------------------------
wdenkd126bfb2003-04-10 11:18:18 +0000202 * Hardware Information Block
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
205#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
206#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkd126bfb2003-04-10 11:18:18 +0000207
208/*-----------------------------------------------------------------------
209 * Cache Configuration
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500212#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkd126bfb2003-04-10 11:18:18 +0000214#endif
215
216/*-----------------------------------------------------------------------
217 * SYPCR - System Protection Control 11-9
218 * SYPCR can only be written once after reset!
219 *-----------------------------------------------------------------------
220 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
221 */
222#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkd126bfb2003-04-10 11:18:18 +0000224 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
225#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkd126bfb2003-04-10 11:18:18 +0000227#endif
228
229/*-----------------------------------------------------------------------
230 * SIUMCR - SIU Module Configuration 11-6
231 *-----------------------------------------------------------------------
232 * PCMCIA config., multi-function pin tri-state
233 */
234#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd126bfb2003-04-10 11:18:18 +0000236#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd126bfb2003-04-10 11:18:18 +0000238#endif /* CONFIG_CAN_DRIVER */
239
240/*-----------------------------------------------------------------------
241 * TBSCR - Time Base Status and Control 11-26
242 *-----------------------------------------------------------------------
243 * Clear Reference Interrupt Status, Timebase freezing enabled
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkd126bfb2003-04-10 11:18:18 +0000246
247/*-----------------------------------------------------------------------
248 * RTCSC - Real-Time Clock Status and Control Register 11-27
249 *-----------------------------------------------------------------------
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkd126bfb2003-04-10 11:18:18 +0000252
253/*-----------------------------------------------------------------------
254 * PISCR - Periodic Interrupt Status and Control 11-31
255 *-----------------------------------------------------------------------
256 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkd126bfb2003-04-10 11:18:18 +0000259
260/*-----------------------------------------------------------------------
261 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
262 *-----------------------------------------------------------------------
263 * Reset PLL lock status sticky bit, timer expired status bit and timer
264 * interrupt status bit
wdenkd126bfb2003-04-10 11:18:18 +0000265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkd126bfb2003-04-10 11:18:18 +0000267
268/*-----------------------------------------------------------------------
269 * SCCR - System Clock and reset Control Register 15-27
270 *-----------------------------------------------------------------------
271 * Set clock output, timebase and RTC source and divider,
272 * power management and some other internal clocks
273 */
274#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd126bfb2003-04-10 11:18:18 +0000276 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
277 SCCR_DFALCD00)
wdenkd126bfb2003-04-10 11:18:18 +0000278
279/*-----------------------------------------------------------------------
280 * PCMCIA stuff
281 *-----------------------------------------------------------------------
282 *
283 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
285#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
286#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
287#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
288#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
289#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
290#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
291#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkd126bfb2003-04-10 11:18:18 +0000292
293/*-----------------------------------------------------------------------
294 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
295 *-----------------------------------------------------------------------
296 */
297
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000298#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkd126bfb2003-04-10 11:18:18 +0000299#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
300
301#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
302#undef CONFIG_IDE_LED /* LED for ide not supported */
303#undef CONFIG_IDE_RESET /* reset for ide not supported */
304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
306#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkd126bfb2003-04-10 11:18:18 +0000307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkd126bfb2003-04-10 11:18:18 +0000309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkd126bfb2003-04-10 11:18:18 +0000311
312/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd126bfb2003-04-10 11:18:18 +0000314
315/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd126bfb2003-04-10 11:18:18 +0000317
318/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkd126bfb2003-04-10 11:18:18 +0000320
321/*-----------------------------------------------------------------------
322 *
323 *-----------------------------------------------------------------------
324 *
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_DER 0
wdenkd126bfb2003-04-10 11:18:18 +0000327
328/*
329 * Init Memory Controller:
330 *
331 * BR0/1 and OR0/1 (FLASH)
332 */
333
334#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
wdenk71f95112003-06-15 22:40:42 +0000335#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
wdenkd126bfb2003-04-10 11:18:18 +0000336
337/* used to re-map FLASH both when starting from SRAM or FLASH:
338 * restrict access enough to keep SRAM working (if any)
339 * but not too much to meddle with FLASH accesses
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
342#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkd126bfb2003-04-10 11:18:18 +0000343
344/*
345 * FLASH timing:
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkd126bfb2003-04-10 11:18:18 +0000348 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkd126bfb2003-04-10 11:18:18 +0000349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
351#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
352#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
355#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
356#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000357
358/*
359 * BR2/3 and OR2/3 (SDRAM)
360 *
361 */
362#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
363#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
364#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
365
366/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkd126bfb2003-04-10 11:18:18 +0000368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
370#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000371
372#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
374#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000375#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
377#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
378#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
379#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkd126bfb2003-04-10 11:18:18 +0000380 BR_PS_8 | BR_MS_UPMB | BR_V )
381#endif /* CONFIG_CAN_DRIVER */
382
383/*
384 * Memory Periodic Timer Prescaler
385 *
386 * The Divider for PTA (refresh timer) configuration is based on an
387 * example SDRAM configuration (64 MBit, one bank). The adjustment to
388 * the number of chip selects (NCS) and the actually needed refresh
389 * rate is done by setting MPTPR.
390 *
391 * PTA is calculated from
392 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
393 *
394 * gclk CPU clock (not bus clock!)
395 * Trefresh Refresh cycle * 4 (four word bursts used)
396 *
397 * 4096 Rows from SDRAM example configuration
398 * 1000 factor s -> ms
399 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
400 * 4 Number of refresh cycles per period
401 * 64 Refresh cycle in ms per number of rows
402 * --------------------------------------------
403 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
404 *
wdenk73a8b272003-06-05 19:27:42 +0000405 * 50 MHz => 50.000.000 / Divider = 98
406 * 66 Mhz => 66.000.000 / Divider = 129
407 * 80 Mhz => 80.000.000 / Divider = 156
408 * 100 Mhz => 100.000.000 / Divider = 195
wdenkd126bfb2003-04-10 11:18:18 +0000409 */
wdenke9132ea2004-04-24 23:23:30 +0000410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
412#define CONFIG_SYS_MAMR_PTA 98
wdenkd126bfb2003-04-10 11:18:18 +0000413
414/*
415 * For 16 MBit, refresh rates could be 31.3 us
416 * (= 64 ms / 2K = 125 / quad bursts).
417 * For a simpler initialization, 15.6 us is used instead.
418 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
420 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkd126bfb2003-04-10 11:18:18 +0000421 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
423#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkd126bfb2003-04-10 11:18:18 +0000424
425/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
427#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkd126bfb2003-04-10 11:18:18 +0000428
429/*
430 * MAMR settings for SDRAM
431 */
432
433/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd126bfb2003-04-10 11:18:18 +0000435 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
436 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
437/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd126bfb2003-04-10 11:18:18 +0000439 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
440 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
441
wdenkd126bfb2003-04-10 11:18:18 +0000442#define CONFIG_SCC1_ENET
443#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200444#define CONFIG_ETHPRIME "SCC"
wdenkd126bfb2003-04-10 11:18:18 +0000445
Heiko Schocher7026ead2010-02-09 15:50:27 +0100446#define CONFIG_HWCONFIG 1
447
wdenkd126bfb2003-04-10 11:18:18 +0000448#endif /* __CONFIG_H */