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Stefan Roese6983fe22008-03-11 16:52:24 +01001/*
2 * (C) Copyright 2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese6983fe22008-03-11 16:52:24 +01006 */
7
8/************************************************************************
9 * canyonlands.h - configuration for Canyonlands (460EX)
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Simon Glass65660412015-02-07 11:51:37 -070014#include <linux/kconfig.h>
15
Stefan Roese6983fe22008-03-11 16:52:24 +010016/*-----------------------------------------------------------------------
17 * High Level Configuration Options
18 *----------------------------------------------------------------------*/
Adam Grahamf09f09d2008-10-08 10:12:53 -070019/*
20 * This config file is used for Canyonlands (460EX) Glacier (460GT)
21 * and Arches dual (460GT)
22 */
23#ifdef CONFIG_CANYONLANDS
Simon Glass0bca2842015-02-07 11:51:36 -070024#define CONFIG_460EX /* Specific PPC460EX */
Stefan Roese490f2042008-06-06 15:55:03 +020025#define CONFIG_HOSTNAME canyonlands
Adam Grahamf09f09d2008-10-08 10:12:53 -070026#else
Simon Glass0bca2842015-02-07 11:51:36 -070027#define CONFIG_460GT /* Specific PPC460GT */
Adam Grahamf09f09d2008-10-08 10:12:53 -070028#ifdef CONFIG_GLACIER
29#define CONFIG_HOSTNAME glacier
30#else
31#define CONFIG_HOSTNAME arches
32#define CONFIG_USE_NETDEV eth1
33#define CONFIG_BD_NUM_CPUS 2
Stefan Roese4c9e8552008-03-19 16:20:49 +010034#endif
Adam Grahamf09f09d2008-10-08 10:12:53 -070035#endif
36
Simon Glass0bca2842015-02-07 11:51:36 -070037#define CONFIG_440
Stefan Roese6983fe22008-03-11 16:52:24 +010038
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#ifndef CONFIG_SYS_TEXT_BASE
40#define CONFIG_SYS_TEXT_BASE 0xFFF80000
41#endif
42
Stefan Roese490f2042008-06-06 15:55:03 +020043/*
44 * Include common defines/options for all AMCC eval boards
45 */
46#include "amcc-common.h"
47
Stefan Roese6983fe22008-03-11 16:52:24 +010048#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
49
Simon Glass0bca2842015-02-07 11:51:36 -070050#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
51#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
52#define CONFIG_MISC_INIT_R /* Call misc_init_r */
53#define CONFIG_BOARD_TYPES /* support board types */
Stefan Roese6983fe22008-03-11 16:52:24 +010054
55/*-----------------------------------------------------------------------
56 * Base addresses -- Note these are effective addresses where the
57 * actual resources get mapped (not physical addresses)
58 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
60#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
61#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
Stefan Roese6983fe22008-03-11 16:52:24 +010062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
64#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
65#define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
Stefan Roese6983fe22008-03-11 16:52:24 +010066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
68#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
69#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
70#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
Stefan Roese6983fe22008-03-11 16:52:24 +010071
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +053072/*
73 * BCSR bits as defined in the Canyonlands board user manual.
74 */
75#define BCSR_USBCTRL_OTG_RST 0x32
76#define BCSR_USBCTRL_HOST_RST 0x01
77#define BCSR_SELECT_PCIE 0x10
78
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
Stefan Roese6983fe22008-03-11 16:52:24 +010080
81/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
Stefan Roese6983fe22008-03-11 16:52:24 +010083
84/* EBC stuff */
Adam Grahamf09f09d2008-10-08 10:12:53 -070085#if !defined(CONFIG_ARCHES)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_BCSR_BASE 0xE1000000
Adam Grahamf09f09d2008-10-08 10:12:53 -070087#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
88#define CONFIG_SYS_FLASH_SIZE (64 << 20)
89#else
90#define CONFIG_SYS_FPGA_BASE 0xE1000000
91#define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
92#define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
93#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
94#define CONFIG_SYS_FLASH_SIZE (32 << 20)
95#endif
96
97#define CONFIG_SYS_NAND_ADDR 0xE0000000
98#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
100#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
Adam Grahamf09f09d2008-10-08 10:12:53 -0700101#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
102 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
Stefan Roese6983fe22008-03-11 16:52:24 +0100103
Dave Mitchellddf45cc2008-11-20 14:09:50 -0600104#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
Wolfgang Denkbf560802010-09-10 23:04:05 +0200106#define CONFIG_SYS_SRAM_SIZE (256 << 10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
Stefan Roese6983fe22008-03-11 16:52:24 +0100108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
Stefan Roese41712b42008-03-05 12:31:53 +0100110
Stefan Roese6983fe22008-03-11 16:52:24 +0100111/*-----------------------------------------------------------------------
112 * Initial RAM & stack pointer (placed in OCM)
113 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200115#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200116#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese6983fe22008-03-11 16:52:24 +0100118
119/*-----------------------------------------------------------------------
120 * Serial Port
121 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +0200122#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100123
Stefan Roese6983fe22008-03-11 16:52:24 +0100124/*-----------------------------------------------------------------------
125 * Environment
126 *----------------------------------------------------------------------*/
127/*
128 * Define here the location of the environment variables (FLASH).
129 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200130#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Felix Radensky26d37f02009-06-22 15:30:42 +0300131#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
Stefan Roese6983fe22008-03-11 16:52:24 +0100133
134/*-----------------------------------------------------------------------
135 * FLASH related
136 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200138#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Simon Glass0bca2842015-02-07 11:51:36 -0700139#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */
Stefan Roese6983fe22008-03-11 16:52:24 +0100140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
142#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
143#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese6983fe22008-03-11 16:52:24 +0100144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
146#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese6983fe22008-03-11 16:52:24 +0100147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
149#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese6983fe22008-03-11 16:52:24 +0100150
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200151#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200152#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200154#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese6983fe22008-03-11 16:52:24 +0100155
156/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200157#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
158#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200159#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese6983fe22008-03-11 16:52:24 +0100160
161/*-----------------------------------------------------------------------
162 * NAND-FLASH related
163 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
166#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese6983fe22008-03-11 16:52:24 +0100167
168/*------------------------------------------------------------------------------
169 * DDR SDRAM
170 *----------------------------------------------------------------------------*/
Adam Grahamf09f09d2008-10-08 10:12:53 -0700171#if !defined(CONFIG_ARCHES)
Stefan Roese71665eb2008-03-03 17:27:02 +0100172/*
173 * NAND booting U-Boot version uses a fixed initialization, since the whole
174 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
175 * code.
176 */
Simon Glass0bca2842015-02-07 11:51:36 -0700177#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
Stefan Roese6983fe22008-03-11 16:52:24 +0100178#define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
Simon Glass0bca2842015-02-07 11:51:36 -0700179#define CONFIG_DDR_ECC /* with ECC support */
Stefan Roese6983fe22008-03-11 16:52:24 +0100180#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700181
182#else /* defined(CONFIG_ARCHES) */
183
184#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
185
186#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
187#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
188#undef CONFIG_PPC4xx_DDR_METHOD_A
189
190/* DDR1/2 SDRAM Device Control Register Data Values */
191/* Memory Queue */
192#define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
193#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
194#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
195#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
196#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
197#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
198#define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
199#define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
200#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
201
202/* SDRAM Controller */
203#define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
204#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
205#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
206#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
207#define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
208#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
209#define CONFIG_SYS_SDRAM0_MODT0 0x01000000
210#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
211#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
212#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
213#define CONFIG_SYS_SDRAM0_CODT 0x00800021
214#define CONFIG_SYS_SDRAM0_RTR 0x06180000
215#define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
216#define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
217#define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
218#define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
219#define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
220#define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
221#define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
222#define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
223#define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
224#define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
225#define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
226#define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
227#define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
228#define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
229#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
230#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
231#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
232#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
233#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
234#define CONFIG_SYS_SDRAM0_DLCR 0x03000091
235#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
236#define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
237#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
238#define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
239#define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
240#define CONFIG_SYS_SDRAM0_MMODE 0x00000432
241#define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
242#endif /* !defined(CONFIG_ARCHES) */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
Stefan Roese6983fe22008-03-11 16:52:24 +0100245
246/*-----------------------------------------------------------------------
247 * I2C
248 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000249#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese6983fe22008-03-11 16:52:24 +0100250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
252#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
253#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
254#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese6983fe22008-03-11 16:52:24 +0100255
Stefan Roese87c0b722009-07-20 06:57:27 +0200256/* I2C bootstrap EEPROM */
Stefan Roese514bab62009-08-17 16:57:53 +0200257#if defined(CONFIG_ARCHES)
258#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
259#else
Stefan Roese87c0b722009-07-20 06:57:27 +0200260#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
Stefan Roese514bab62009-08-17 16:57:53 +0200261#endif
Stefan Roese87c0b722009-07-20 06:57:27 +0200262#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
263#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
264
Stefan Roese6983fe22008-03-11 16:52:24 +0100265/* I2C SYSMON (LM75, AD7414 is almost compatible) */
Simon Glass0bca2842015-02-07 11:51:36 -0700266#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
267#define CONFIG_DTT_AD7414 /* use AD7414 */
Stefan Roese6983fe22008-03-11 16:52:24 +0100268#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_DTT_MAX_TEMP 70
270#define CONFIG_SYS_DTT_LOW_TEMP -30
271#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese6983fe22008-03-11 16:52:24 +0100272
Adam Grahamf09f09d2008-10-08 10:12:53 -0700273#if defined(CONFIG_ARCHES)
274#define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
275#endif
276
277#if !defined(CONFIG_ARCHES)
Stefan Roese6983fe22008-03-11 16:52:24 +0100278/* RTC configuration */
Simon Glass0bca2842015-02-07 11:51:36 -0700279#define CONFIG_RTC_M41T62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Adam Grahamf09f09d2008-10-08 10:12:53 -0700281#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100282
283/*-----------------------------------------------------------------------
284 * Ethernet
285 *----------------------------------------------------------------------*/
Simon Glass0bca2842015-02-07 11:51:36 -0700286#define CONFIG_IBM_EMAC4_V4
Adam Grahamf09f09d2008-10-08 10:12:53 -0700287
Stefan Roese4c9e8552008-03-19 16:20:49 +0100288#define CONFIG_HAS_ETH0
289#define CONFIG_HAS_ETH1
Adam Grahamf09f09d2008-10-08 10:12:53 -0700290
291#if !defined(CONFIG_ARCHES)
292#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
293#define CONFIG_PHY1_ADDR 1
Stefan Roese4c9e8552008-03-19 16:20:49 +0100294/* Only Glacier (460GT) has 4 EMAC interfaces */
295#ifdef CONFIG_460GT
296#define CONFIG_PHY2_ADDR 2
297#define CONFIG_PHY3_ADDR 3
298#define CONFIG_HAS_ETH2
299#define CONFIG_HAS_ETH3
300#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100301
Adam Grahamf09f09d2008-10-08 10:12:53 -0700302#else /* defined(CONFIG_ARCHES) */
303
304#define CONFIG_FIXED_PHY 0xFFFFFFFF
305#define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
306#define CONFIG_PHY1_ADDR 0
307#define CONFIG_PHY2_ADDR 1
308#define CONFIG_HAS_ETH2
309
310#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
311 {devnum, speed, duplex}
312#define CONFIG_SYS_FIXED_PHY_PORTS \
313 CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
314
315#define CONFIG_M88E1112_PHY
316
317/*
318 * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
319 * used by CONFIG_PHYx_ADDR
320 */
321#define CONFIG_GPCS_PHY_ADDR 0xA
322#define CONFIG_GPCS_PHY1_ADDR 0xB
323#define CONFIG_GPCS_PHY2_ADDR 0xC
324#endif /* !defined(CONFIG_ARCHES) */
325
Simon Glass0bca2842015-02-07 11:51:36 -0700326#define CONFIG_PHY_RESET /* reset phy upon startup */
327#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
328#define CONFIG_PHY_DYNAMIC_ANEG
Stefan Roese6983fe22008-03-11 16:52:24 +0100329
Stefan Roese41712b42008-03-05 12:31:53 +0100330/*-----------------------------------------------------------------------
331 * USB-OHCI
332 *----------------------------------------------------------------------*/
Stefan Roese4c9e8552008-03-19 16:20:49 +0100333/* Only Canyonlands (460EX) has USB */
334#ifdef CONFIG_460EX
Stefan Roese41712b42008-03-05 12:31:53 +0100335#define CONFIG_USB_OHCI_NEW
336#define CONFIG_USB_STORAGE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
338#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
339#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
340#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
341#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
342#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Rupjyoti Sarmah17a68442010-07-07 18:14:48 +0530343#define CONFIG_SYS_USB_OHCI_BOARD_INIT
Stefan Roese4c9e8552008-03-19 16:20:49 +0100344#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100345
Stefan Roese490f2042008-06-06 15:55:03 +0200346/*
347 * Default environment variables
348 */
Adam Grahamf09f09d2008-10-08 10:12:53 -0700349#if !defined(CONFIG_ARCHES)
350#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200351 CONFIG_AMCC_DEF_ENV \
352 CONFIG_AMCC_DEF_ENV_POWERPC \
353 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese6983fe22008-03-11 16:52:24 +0100354 "kernel_addr=fc000000\0" \
Stefan Roese5d40d442008-04-22 14:14:20 +0200355 "fdt_addr=fc1e0000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100356 "ramdisk_addr=fc200000\0" \
Stefan Roese6983fe22008-03-11 16:52:24 +0100357 "pciconfighost=1\0" \
358 "pcie_mode=RP:RP\0" \
359 ""
Adam Grahamf09f09d2008-10-08 10:12:53 -0700360#else /* defined(CONFIG_ARCHES) */
361#define CONFIG_EXTRA_ENV_SETTINGS \
362 CONFIG_AMCC_DEF_ENV \
363 CONFIG_AMCC_DEF_ENV_POWERPC \
364 CONFIG_AMCC_DEF_ENV_NOR_UPD \
365 "kernel_addr=fe000000\0" \
366 "fdt_addr=fe1e0000\0" \
367 "ramdisk_addr=fe200000\0" \
368 "pciconfighost=1\0" \
369 "pcie_mode=RP:RP\0" \
370 "ethprime=ppc_4xx_eth1\0" \
371 ""
372#endif /* !defined(CONFIG_ARCHES) */
Stefan Roese6983fe22008-03-11 16:52:24 +0100373
374/*
Stefan Roese490f2042008-06-06 15:55:03 +0200375 * Commands additional to the ones defined in amcc-common.h
Stefan Roese6983fe22008-03-11 16:52:24 +0100376 */
Stefan Roese87c0b722009-07-20 06:57:27 +0200377#define CONFIG_CMD_CHIP_CONFIG
Adam Grahamf09f09d2008-10-08 10:12:53 -0700378#if defined(CONFIG_ARCHES)
379#define CONFIG_CMD_DTT
380#define CONFIG_CMD_PCI
381#define CONFIG_CMD_SDRAM
382#elif defined(CONFIG_CANYONLANDS)
383#define CONFIG_CMD_DATE
384#define CONFIG_CMD_DTT
Adam Grahamf09f09d2008-10-08 10:12:53 -0700385#define CONFIG_CMD_NAND
386#define CONFIG_CMD_PCI
Kazuaki Ichinohee405afa2009-06-12 18:10:12 +0900387#define CONFIG_CMD_SATA
Adam Grahamf09f09d2008-10-08 10:12:53 -0700388#define CONFIG_CMD_SDRAM
Adam Grahamf09f09d2008-10-08 10:12:53 -0700389#elif defined(CONFIG_GLACIER)
Stefan Roese6983fe22008-03-11 16:52:24 +0100390#define CONFIG_CMD_DATE
Stefan Roese6983fe22008-03-11 16:52:24 +0100391#define CONFIG_CMD_DTT
Stefan Roese6983fe22008-03-11 16:52:24 +0100392#define CONFIG_CMD_NAND
Stefan Roese6983fe22008-03-11 16:52:24 +0100393#define CONFIG_CMD_PCI
Stefan Roese6983fe22008-03-11 16:52:24 +0100394#define CONFIG_CMD_SDRAM
Adam Grahamf09f09d2008-10-08 10:12:53 -0700395#else
396#error "board type not defined"
Stefan Roese4c9e8552008-03-19 16:20:49 +0100397#endif
Stefan Roese41712b42008-03-05 12:31:53 +0100398
399/* Partitions */
400#define CONFIG_MAC_PARTITION
401#define CONFIG_DOS_PARTITION
402#define CONFIG_ISO_PARTITION
Stefan Roese6983fe22008-03-11 16:52:24 +0100403
404/*-----------------------------------------------------------------------
Stefan Roese6983fe22008-03-11 16:52:24 +0100405 * PCI stuff
406 *----------------------------------------------------------------------*/
407/* General PCI */
408#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000409#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese6983fe22008-03-11 16:52:24 +0100410#define CONFIG_PCI_PNP /* do pci plug-and-play */
411#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
412#define CONFIG_PCI_CONFIG_HOST_BRIDGE
413
414/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
416#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese6983fe22008-03-11 16:52:24 +0100417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
419#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
Stefan Roese6983fe22008-03-11 16:52:24 +0100420
Adam Grahamf09f09d2008-10-08 10:12:53 -0700421#ifdef CONFIG_460GT
422#if defined(CONFIG_ARCHES)
423/*-----------------------------------------------------------------------
424 * RapidIO I/O and Registers
425 *----------------------------------------------------------------------*/
426#define CONFIG_RAPIDIO
427#define CONFIG_SYS_460GT_SRIO_ERRATA_1
428
429#define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
430#define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
431#define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
432#define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
433#define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
434
435#define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
436#define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
437#define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
438#define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
439
440#define CONFIG_SYS_I2ODMA_BASE 0xCF000000
441#define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
442
443#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
444#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
445#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
446#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
447#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
448#endif /* CONFIG_ARCHES */
449#endif /* CONFIG_460GT */
450
Kazuaki Ichinohee405afa2009-06-12 18:10:12 +0900451/*
452 * SATA driver setup
453 */
454#ifdef CONFIG_CMD_SATA
455#define CONFIG_SATA_DWC
456#define CONFIG_LIBATA
457#define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
458#define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
459#define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
460/* Convert sectorsize to wordsize */
461#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
462#endif
463
Stefan Roese6983fe22008-03-11 16:52:24 +0100464/*-----------------------------------------------------------------------
465 * External Bus Controller (EBC) Setup
466 *----------------------------------------------------------------------*/
467
468/*
469 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
470 * boot EBC mapping only supports a maximum of 16MBytes
471 * (4.ff00.0000 - 4.ffff.ffff).
472 * To solve this problem, the FLASH has to get remapped to another
473 * EBC address which accepts bigger regions:
474 *
475 * 0xfc00.0000 -> 4.cc00.0000
Adam Grahamf09f09d2008-10-08 10:12:53 -0700476 *
477 * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
478 * remapped to:
479 *
480 * 0xfe00.0000 -> 4.ce00.0000
Stefan Roese6983fe22008-03-11 16:52:24 +0100481 */
482
483/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_EBC_PB0AP 0x10055e00
485#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
Stefan Roese6983fe22008-03-11 16:52:24 +0100486
Adam Grahamf09f09d2008-10-08 10:12:53 -0700487#if !defined(CONFIG_ARCHES)
Stefan Roese6983fe22008-03-11 16:52:24 +0100488/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_EBC_PB3AP 0x018003c0
490#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
Stefan Roese71665eb2008-03-03 17:27:02 +0100491#endif
492
Adam Grahamf09f09d2008-10-08 10:12:53 -0700493#if !defined(CONFIG_ARCHES)
Stefan Roese71665eb2008-03-03 17:27:02 +0100494/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_EBC_PB2AP 0x00804240
496#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
Stefan Roese6983fe22008-03-11 16:52:24 +0100497
Adam Grahamf09f09d2008-10-08 10:12:53 -0700498#else /* defined(CONFIG_ARCHES) */
499
500/* Memory Bank 1 (FPGA) initialization */
501#define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
502#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
503#endif /* !defined(CONFIG_ARCHES) */
504
Stefan Roese916ed942009-10-29 18:37:45 +0100505#define CONFIG_SYS_EBC_CFG 0xbfc00000
Stefan Roese6983fe22008-03-11 16:52:24 +0100506
507/*
Stefan Roese3befd852008-10-25 06:45:31 +0200508 * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
509 * pin multiplexing correctly
510 */
511#if defined(CONFIG_ARCHES)
512#define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */
513#else
514#define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */
515#endif
516
517/*
Stefan Roese6983fe22008-03-11 16:52:24 +0100518 * PPC4xx GPIO Configuration
519 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100520#ifdef CONFIG_460EX
521/* 460EX: Use USB configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100523{ \
524/* GPIO Core 0 */ \
Stefan Roese41712b42008-03-05 12:31:53 +0100525{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
526{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
527{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
528{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
529{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
530{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
531{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
532{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
533{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
534{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
535{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
536{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
537{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
538{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
539{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
540{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
541{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
542{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
543{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
544{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
545{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
546{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
Stefan Roese6983fe22008-03-11 16:52:24 +0100547{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
548{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
549{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
550{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
551{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
552{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
553{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
554{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
555{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
556{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
557}, \
558{ \
559/* GPIO Core 1 */ \
560{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
561{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
562{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
563{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
564{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
565{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
566{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
567{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
568{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
569{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
570{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
571{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
572{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
573{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
574{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
575{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
576{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
577{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
578{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
579{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
580{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
581{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
582{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
583{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
584{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
585{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
586{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
587{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
588{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
589{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
590{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
591{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
592} \
593}
Stefan Roese4c9e8552008-03-19 16:20:49 +0100594#else
595/* 460GT: Use EMAC2+3 configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100597{ \
598/* GPIO Core 0 */ \
599{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
600{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
601{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
602{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
603{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
604{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
605{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
606{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
607{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
608{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
609{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
610{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
611{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
612{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
613{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
614{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
615{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
616{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
617{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
618{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
619{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
620{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
621{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
622{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
623{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
624{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
625{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
626{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
627{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
628{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
629{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
630{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
631}, \
632{ \
633/* GPIO Core 1 */ \
634{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
635{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
636{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
637{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
638{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
639{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
640{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
641{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
642{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
643{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
644{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
Stefan Roese3befd852008-10-25 06:45:31 +0200645{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
Stefan Roese4c9e8552008-03-19 16:20:49 +0100646{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
647{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
648{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
649{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
650{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
651{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
652{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
653{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
654{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
655{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
656{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
657{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
658{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
659{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
660{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
661{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
662{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
663{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
664{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
665{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
666} \
667}
668#endif
Stefan Roese6983fe22008-03-11 16:52:24 +0100669
Stefan Roese6983fe22008-03-11 16:52:24 +0100670#endif /* __CONFIG_H */