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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * (C) Copyright 2004
8 * ARM Ltd.
9 * Philippe Robin, <philippe.robin@arm.com>
10 * Configuration for Versatile PB.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_VERSATILE 1 /* in Versatile Platform Board */
40#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */
41
42
43#define CFG_MEMTEST_START 0x100000
44#define CFG_MEMTEST_END 0x10000000
45#define CFG_HZ (1000000 / 256)
46#define CFG_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */
47
48#define CFG_TIMER_INTERVAL 10000
49#define CFG_TIMER_RELOAD (CFG_TIMER_INTERVAL >> 4) /* Divide by 16 */
50#define CFG_TIMER_CTRL 0x84 /* Enable, Clock / 16 */
51
52/*
53 * control registers
54 */
55#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */
56
57/*
58 * System controller bit assignment
59 */
60#define VERSATILE_REFCLK 0
61#define VERSATILE_TIMCLK 1
62
63#define VERSATILE_TIMER1_EnSel 15
64#define VERSATILE_TIMER2_EnSel 17
65#define VERSATILE_TIMER3_EnSel 19
66#define VERSATILE_TIMER4_EnSel 21
67
68#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
69#define CONFIG_SETUP_MEMORY_TAGS 1
70#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */
71/*
72 * Size of malloc() pool
73 */
74#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenk42dfe7a2004-03-14 22:25:36 +000075#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk3d3befa2004-03-14 15:06:13 +000076
77/*
78 * Hardware drivers
79 */
80
81#define CONFIG_DRIVER_SMC91111
82#define CONFIG_SMC_USE_32_BIT
83#define CONFIG_SMC91111_BASE 0x10010000
84#undef CONFIG_SMC91111_EXT_PHY
85
86/*
87 * NS16550 Configuration
88 */
89#define CFG_PL011_SERIAL
wdenk6705d812004-08-02 23:22:59 +000090#define CONFIG_PL011_CLOCK 24000000
91#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
wdenk3d3befa2004-03-14 15:06:13 +000092#define CONFIG_CONS_INDEX 0
wdenk6705d812004-08-02 23:22:59 +000093
wdenk3d3befa2004-03-14 15:06:13 +000094#define CONFIG_BAUDRATE 38400
95#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
96#define CFG_SERIAL0 0x101F1000
97#define CFG_SERIAL1 0x101F2000
98
99#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY)
100
wdenk42dfe7a2004-03-14 22:25:36 +0000101/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */
wdenk3d3befa2004-03-14 15:06:13 +0000102
103#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
104
105/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
106#include <cmd_confdefs.h>
107
108#define CONFIG_BOOTDELAY 2
wdenk0b8fa032004-04-25 14:37:29 +0000109#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0"
wdenk42dfe7a2004-03-14 22:25:36 +0000110/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */
wdenk3d3befa2004-03-14 15:06:13 +0000111
112/*
113 * Static configuration when assigning fixed address
114 */
wdenk42dfe7a2004-03-14 22:25:36 +0000115/*#define CONFIG_NETMASK 255.255.255.0 /--* talk on MY local net */
116/*#define CONFIG_IPADDR xx.xx.xx.xx /--* static IP I currently own */
117/*#define CONFIG_SERVERIP xx.xx.xx.xx /--* current IP of my dev pc */
wdenk3d3befa2004-03-14 15:06:13 +0000118#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */
119
120
121/*
122 * Miscellaneous configurable options
123 */
124#define CFG_LONGHELP /* undef to save memory */
125#define CFG_PROMPT "Versatile # " /* Monitor Command Prompt */
126#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
127/* Print Buffer Size */
128#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
129#define CFG_MAXARGS 16 /* max number of command args */
130#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
131
132#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
133#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
134
135/*-----------------------------------------------------------------------
136 * Stack sizes
137 *
138 * The stack sizes are set up in start.S using the settings below
139 */
140#define CONFIG_STACKSIZE (128*1024) /* regular stack */
141#ifdef CONFIG_USE_IRQ
142#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
143#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
144#endif
145
146/*-----------------------------------------------------------------------
147 * Physical Memory Map
148 */
149#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
150#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
151#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
152
153#define CFG_FLASH_BASE 0x34000000
154
155/*-----------------------------------------------------------------------
156 * FLASH and environment organization
157 */
158#define CFG_ENV_IS_NOWHERE
159#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
160#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */
161/* timeout values are in ticks */
162#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
163#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
164#define CFG_MAX_FLASH_SECT 128
165#define CFG_ENV_SIZE 32768
166
167#define PHYS_FLASH_1 (CFG_FLASH_BASE)
168
169#endif /* __CONFIG_H */