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Wolfgang Grandegger3f467522012-02-08 22:33:25 +00001/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <common.h>
17#include <usb.h>
18#include <errno.h>
19#include <linux/compiler.h>
20#include <usb/ehci-fsl.h>
21#include <asm/io.h>
22#include <asm/arch/imx-regs.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/mx6x_pins.h>
Troy Kiskyaf2a35f2012-07-19 08:18:22 +000025#include <asm/imx-common/iomux-v3.h>
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000026
27#include "ehci.h"
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000028
29#define USB_OTGREGS_OFFSET 0x000
30#define USB_H1REGS_OFFSET 0x200
31#define USB_H2REGS_OFFSET 0x400
32#define USB_H3REGS_OFFSET 0x600
33#define USB_OTHERREGS_OFFSET 0x800
34
35#define USB_H1_CTRL_OFFSET 0x04
36
37#define USBPHY_CTRL 0x00000030
38#define USBPHY_CTRL_SET 0x00000034
39#define USBPHY_CTRL_CLR 0x00000038
40#define USBPHY_CTRL_TOG 0x0000003c
41
42#define USBPHY_PWD 0x00000000
43#define USBPHY_CTRL_SFTRST 0x80000000
44#define USBPHY_CTRL_CLKGATE 0x40000000
45#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
46#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
47
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000048#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
49#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
50
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000051#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
52#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
53#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
54#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
55
56
57#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
58#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
59
60/* USBCMD */
61#define UH1_USBCMD_OFFSET 0x140
62#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
63#define UCMD_RESET (1 << 1) /* controller reset */
64
65static void usbh1_internal_phy_clock_gate(int on)
66{
67 void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
68
69 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
70 __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
71}
72
73static void usbh1_power_config(void)
74{
Wolfgang Grandegger3f29d962012-05-02 04:36:39 +000075 struct anatop_regs __iomem *anatop =
76 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000077 /*
78 * Some phy and power's special controls for host1
79 * 1. The external charger detector needs to be disabled
80 * or the signal at DP will be poor
81 * 2. The PLL's power and output to usb for host 1
82 * is totally controlled by IC, so the Software only needs
83 * to enable them at initializtion.
84 */
85 __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
86 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
Fabio Estevam522b2a02012-03-19 12:36:10 +000087 &anatop->usb2_chrg_detect);
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000088
89 __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
Wolfgang Grandegger3f29d962012-05-02 04:36:39 +000090 &anatop->usb2_pll_480_ctrl_clr);
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000091
92 __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
93 ANADIG_USB2_PLL_480_CTRL_POWER |
94 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
Fabio Estevam522b2a02012-03-19 12:36:10 +000095 &anatop->usb2_pll_480_ctrl_set);
Wolfgang Grandegger3f467522012-02-08 22:33:25 +000096}
97
98static int usbh1_phy_enable(void)
99{
100 void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
101 void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
102 void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
103 USB_H1REGS_OFFSET +
104 UH1_USBCMD_OFFSET);
105 u32 val;
106
107 /* Stop then Reset */
108 val = __raw_readl(usb_cmd);
109 val &= ~UCMD_RUN_STOP;
110 __raw_writel(val, usb_cmd);
111 while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
112 ;
113
114 val = __raw_readl(usb_cmd);
115 val |= UCMD_RESET;
116 __raw_writel(val, usb_cmd);
117 while (__raw_readl(usb_cmd) & UCMD_RESET)
118 ;
119
120 /* Reset USBPHY module */
121 val = __raw_readl(phy_ctrl);
122 val |= USBPHY_CTRL_SFTRST;
123 __raw_writel(val, phy_ctrl);
124 udelay(10);
125
126 /* Remove CLKGATE and SFTRST */
127 val = __raw_readl(phy_ctrl);
128 val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
129 __raw_writel(val, phy_ctrl);
130 udelay(10);
131
132 /* Power up the PHY */
133 __raw_writel(0, phy_reg + USBPHY_PWD);
134 /* enable FS/LS device */
135 val = __raw_readl(phy_reg + USBPHY_CTRL);
136 val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
137 __raw_writel(val, phy_reg + USBPHY_CTRL);
138
139 return 0;
140}
141
142static void usbh1_oc_config(void)
143{
144 void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
145 void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
146 u32 val;
147
148 val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
149#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
150 /* mx6qarm2 seems to required a different setting*/
151 val &= ~UCTRL_OVER_CUR_POL;
152#else
153 val |= UCTRL_OVER_CUR_POL;
154#endif
155 __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
156
157 val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
158 val |= UCTRL_OVER_CUR_DIS;
159 __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
160}
161
Lucas Stach676ae062012-09-26 00:14:35 +0200162int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
Wolfgang Grandegger3f467522012-02-08 22:33:25 +0000163{
164 struct usb_ehci *ehci;
165
166 enable_usboh3_clk(1);
167 mdelay(1);
168
169 /* Do board specific initialization */
170 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
171
172#if CONFIG_MXC_USB_PORT == 1
173 /* USB Host 1 */
174 usbh1_power_config();
175 usbh1_oc_config();
176 usbh1_internal_phy_clock_gate(1);
177 usbh1_phy_enable();
178#else
179#error "MXC USB port not yet supported"
180#endif
181
182 ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
183 (0x200 * CONFIG_MXC_USB_PORT));
Lucas Stach676ae062012-09-26 00:14:35 +0200184 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
185 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
186 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
Wolfgang Grandegger3f467522012-02-08 22:33:25 +0000187 setbits_le32(&ehci->usbmode, CM_HOST);
188
189 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
190 setbits_le32(&ehci->portsc, USB_EN);
191
192 mdelay(10);
193
194 return 0;
195}
196
Lucas Stach676ae062012-09-26 00:14:35 +0200197int ehci_hcd_stop(int index)
Wolfgang Grandegger3f467522012-02-08 22:33:25 +0000198{
199 return 0;
200}