blob: 7c55744ac7ed7f2c06b426945346dd0b1a7d9d62 [file] [log] [blame]
Frank Wunderlich8ad2fc42020-08-10 16:45:46 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7622.dtsi"
9#include "mt7622-u-boot.dtsi"
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "mt7622-bpi-r64";
15 compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
16 chosen {
17 stdout-path = &uart0;
18 tick-timer = &timer0;
19 };
20
21 aliases {
22 spi0 = &snfi;
23 };
24
25 memory@40000000 {
26 device_type = "memory";
27 reg = <0x40000000 0x40000000>;
28 };
29
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
34 regulator-max-microvolt = <1800000>;
35 regulator-boot-on;
36 regulator-always-on;
37 };
38
39 reg_3p3v: regulator-3p3v {
40 compatible = "regulator-fixed";
41 regulator-name = "fixed-3.3V";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-boot-on;
45 regulator-always-on;
46 };
47};
48
Frank Wunderlichf08c2c22020-08-14 09:10:17 +020049&pcie {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
52 status = "okay";
53
54 pcie@0,0 {
55 status = "okay";
56 };
57
58 pcie@1,0 {
59 status = "okay";
60 };
61};
Frank Wunderlich8ad2fc42020-08-10 16:45:46 +020062
63&pinctrl {
Frank Wunderlichf08c2c22020-08-14 09:10:17 +020064 pcie0_pins: pcie0-pins {
65 mux {
66 function = "pcie";
67 groups = "pcie0_pad_perst",
68 "pcie0_1_waken",
69 "pcie0_1_clkreq";
70 };
71 };
72
73 pcie1_pins: pcie1-pins {
74 mux {
75 function = "pcie";
76 groups = "pcie1_pad_perst",
77 "pcie1_0_waken",
78 "pcie1_0_clkreq";
79 };
80 };
81
Frank Wunderlich8ad2fc42020-08-10 16:45:46 +020082 snfi_pins: snfi-pins {
83 mux {
84 function = "flash";
85 groups = "snfi";
86 };
87 };
88
89 snor_pins: snor-pins {
90 mux {
91 function = "flash";
92 groups = "spi_nor";
93 };
94 };
95
96 uart0_pins: uart0 {
97 mux {
98 function = "uart";
99 groups = "uart0_0_tx_rx" ;
100 };
101 };
102
103 pwm_pins: pwm1 {
104 mux {
105 function = "pwm";
106 groups = "pwm_ch1_0" ;
107 };
108 };
109
110 watchdog_pins: watchdog-default {
111 mux {
112 function = "watchdog";
113 groups = "watchdog";
114 };
115 };
116
117 mmc0_pins_default: mmc0default {
118 mux {
119 function = "emmc";
120 groups = "emmc";
121 };
122
123 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
124 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
125 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
126 */
127 conf-cmd-dat {
128 pins = "NDL0", "NDL1", "NDL2",
129 "NDL3", "NDL4", "NDL5",
130 "NDL6", "NDL7", "NRB";
131 input-enable;
132 bias-pull-up;
133 };
134
135 conf-clk {
136 pins = "NCLE";
137 bias-pull-down;
138 };
139
140 };
141
142 mmc1_pins_default: mmc1default {
143 mux {
144 function = "sd";
145 groups = "sd_0";
146 };
147 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
148 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
149 * DAT2, DAT3, CMD, CLK for SD respectively.
150 */
151 conf-cmd-data {
152 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
153 "I2S2_IN","I2S4_OUT";
154 input-enable;
155 drive-strength = <8>;
156 bias-pull-up;
157 };
158 conf-clk {
159 pins = "I2S3_OUT";
160 drive-strength = <12>;
161 bias-pull-down;
162 };
163 conf-cd {
164 pins = "TXD3";
165 bias-pull-up;
166 };
167
168 };
169};
170
171&snfi {
172 pinctrl-names = "default", "snfi";
173 pinctrl-0 = <&snor_pins>;
174 pinctrl-1 = <&snfi_pins>;
175 status = "okay";
176
177 spi-flash@0{
178 compatible = "jedec,spi-nor";
179 reg = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700180 bootph-all;
Frank Wunderlich8ad2fc42020-08-10 16:45:46 +0200181 };
182};
183
184&uart0 {
Frank Wunderlich8ad2fc42020-08-10 16:45:46 +0200185 status = "okay";
186};
187
188&pwm {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pwm_pins>;
191 status = "okay";
192};
193
194&mmc0 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&mmc0_pins_default>;
197 status = "okay";
198 bus-width = <8>;
199 max-frequency = <50000000>;
200 cap-sd-highspeed;
201 vmmc-supply = <&reg_3p3v>;
202 vqmmc-supply = <&reg_3p3v>;
203 non-removable;
204};
205
206&mmc1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&mmc1_pins_default>;
209 status = "okay";
210 bus-width = <4>;
211 max-frequency = <50000000>;
212 cap-sd-highspeed;
213 r_smpl = <1>;
214 vmmc-supply = <&reg_3p3v>;
215 vqmmc-supply = <&reg_3p3v>;
216};
217
218&watchdog {
219 pinctrl-names = "default";
220 pinctrl-0 = <&watchdog_pins>;
221 status = "okay";
222};
223
224&eth {
225 status = "okay";
226 mediatek,gmac-id = <0>;
227 phy-mode = "sgmii";
228 mediatek,switch = "mt7531";
229 reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;
230
231 fixed-link {
232 speed = <1000>;
233 full-duplex;
234 };
235};
Frank Wunderlich7cf85372020-08-13 10:20:48 +0200236
237&gpio {
238 /*gpio 90 for setting mode to sata*/
239 asm_sel {
240 gpio-hog;
241 gpios = <90 GPIO_ACTIVE_HIGH>;
242 output-low;
243 };
244};
Frank Wunderlicha13666b2020-08-20 16:37:57 +0200245
246&ssusb {
247 status = "okay";
248};
249
250&u3phy {
251 status = "okay";
252};