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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 6786ce1ce14feb4d02854a0c04bc0cce505be46e / . / include / configs / sama5d3xek.h
blob: 4f579ad9c5616f7c9d193de3544b8590b626693e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]2/*
3 * Configuation settings for the SAMA5D3xEK board.
4 *
5 * Copyright (C) 2012 - 2013 Atmel
6 *
7 * based on at91sam9m10g45ek.h by:
8 * Stelian Pop <stelian@popies.net>
9 * Lead Tech Design <www.leadtechdesign.com>
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Wu, Joshb2d387b2015-03-30 14:51:19 +0800[diff] [blame]15#include "at91-sama5_common.h"
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]16
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]17/*
18 * This needs to be defined for the OHCI code to work but it is defined as
19 * ATMEL_ID_UHPHS in the CPU specific header files.
20 */
Wenyou Yange61ed482017-09-14 11:07:42 +0800[diff] [blame]21#define ATMEL_ID_UHP 32
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]22
23/*
24 * Specify the clock enable bit in the PMC_SCER register.
25 */
Wenyou Yange61ed482017-09-14 11:07:42 +0800[diff] [blame]26#define ATMEL_PMC_UHP (1 << 6)
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]27
Bo Shend6b79432014-07-18 16:43:08 +0800[diff] [blame]28/* NOR flash */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900[diff] [blame]29#ifdef CONFIG_MTD_NOR_FLASH
Tom Rini65cc0e22022-11-16 13:10:41 -0500[diff] [blame]30#define CFG_SYS_FLASH_BASE 0x10000000
Bo Shend6b79432014-07-18 16:43:08 +0800[diff] [blame]31#endif
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]32
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]33/* SDRAM */
Tom Riniaa6e94d2022-11-16 13:10:37 -0500[diff] [blame]34#define CFG_SYS_SDRAM_BASE 0x20000000
35#define CFG_SYS_SDRAM_SIZE 0x20000000
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]36
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]37/* SerialFlash */
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]38
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]39/* NAND flash */
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]40#ifdef CONFIG_CMD_NAND
Tom Rini4e590942022-11-12 17:36:51 -0500[diff] [blame]41#define CFG_SYS_NAND_BASE 0x60000000
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]42/* our ALE is AD21 */
Tom Rini4e590942022-11-12 17:36:51 -0500[diff] [blame]43#define CFG_SYS_NAND_MASK_ALE (1 << 21)
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]44/* our CLE is AD22 */
Tom Rini4e590942022-11-12 17:36:51 -0500[diff] [blame]45#define CFG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rini8f1a80e2017-07-28 21:31:42 -0400[diff] [blame]46#endif
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]47
Bo Shenc5e88852013-11-15 11:12:38 +0800[diff] [blame]48/* SPL */
Bo Shenc5e88852013-11-15 11:12:38 +0800[diff] [blame]49
Bo Shen3225f342013-05-12 22:40:54 +0000[diff] [blame]50#endif