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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 67e6c540a098ee5ecb3fdf0b332d9a63b00fdbd7 / . / arch / arm / lib / asm-offsets.c
blob: 22fd541f9a289df7c0339c07734cc9756d5fa4a3 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]2/*
3 * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
4 *
5 * This program is used to generate definitions needed by
6 * assembly language modules.
7 *
8 * We use the technique used in the OSF Mach kernel code:
9 * generate asm statements containing #defines,
10 * compile this file to assembler, and then extract the
11 * #defines from the assembly-language output.
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]12 */
13
14#include <common.h>
15#include <linux/kbuild.h>
Masahiro Yamadac54bcf62017-04-14 11:10:23 +0900[diff] [blame]16#include <linux/arm-smccc.h>
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]17
Tom Rini8ba59602021-09-09 07:54:50 -0400[diff] [blame]18#if defined(CONFIG_MX27) \
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]19 || defined(CONFIG_MX51) || defined(CONFIG_MX53)
20#include <asm/arch/imx-regs.h>
21#endif
22
23int main(void)
24{
25 /*
26 * TODO : Check if each entry in this file is really necessary.
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]27 * - struct esdramc_regs
28 * - struct max_regs
29 * - struct aips_regs
30 * - struct aipi_regs
31 * - struct clkctl
32 * - struct dpll
33 * are used only for generating asm-offsets.h.
34 * It means their offset addresses are referenced only from assembly
35 * code. Is it better to define the macros directly in headers?
36 */
37
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]38#if defined(CONFIG_MX27)
39 DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
40 DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
41 DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
42 DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
43
44 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
45 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
46 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
47 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
48 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
49 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
50 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
51
52 DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
53 DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
54 DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
55 DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
56 DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
57
58 DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
59 offsetof(struct system_control_regs, gpcr));
60 DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
61 offsetof(struct system_control_regs, fmcr));
62#endif
63
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]64#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
65 /* Round up to make sure size gives nice stack alignment */
66 DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
67 DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
68 DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
69 DEFINE(CLKCTL_CCSR, offsetof(struct clkctl, ccsr));
70 DEFINE(CLKCTL_CACRR, offsetof(struct clkctl, cacrr));
71 DEFINE(CLKCTL_CBCDR, offsetof(struct clkctl, cbcdr));
72 DEFINE(CLKCTL_CBCMR, offsetof(struct clkctl, cbcmr));
73 DEFINE(CLKCTL_CSCMR1, offsetof(struct clkctl, cscmr1));
74 DEFINE(CLKCTL_CSCMR2, offsetof(struct clkctl, cscmr2));
75 DEFINE(CLKCTL_CSCDR1, offsetof(struct clkctl, cscdr1));
76 DEFINE(CLKCTL_CS1CDR, offsetof(struct clkctl, cs1cdr));
77 DEFINE(CLKCTL_CS2CDR, offsetof(struct clkctl, cs2cdr));
78 DEFINE(CLKCTL_CDCDR, offsetof(struct clkctl, cdcdr));
79 DEFINE(CLKCTL_CHSCCDR, offsetof(struct clkctl, chsccdr));
80 DEFINE(CLKCTL_CSCDR2, offsetof(struct clkctl, cscdr2));
81 DEFINE(CLKCTL_CSCDR3, offsetof(struct clkctl, cscdr3));
82 DEFINE(CLKCTL_CSCDR4, offsetof(struct clkctl, cscdr4));
83 DEFINE(CLKCTL_CWDR, offsetof(struct clkctl, cwdr));
84 DEFINE(CLKCTL_CDHIPR, offsetof(struct clkctl, cdhipr));
85 DEFINE(CLKCTL_CDCR, offsetof(struct clkctl, cdcr));
86 DEFINE(CLKCTL_CTOR, offsetof(struct clkctl, ctor));
87 DEFINE(CLKCTL_CLPCR, offsetof(struct clkctl, clpcr));
88 DEFINE(CLKCTL_CISR, offsetof(struct clkctl, cisr));
89 DEFINE(CLKCTL_CIMR, offsetof(struct clkctl, cimr));
90 DEFINE(CLKCTL_CCOSR, offsetof(struct clkctl, ccosr));
91 DEFINE(CLKCTL_CGPR, offsetof(struct clkctl, cgpr));
92 DEFINE(CLKCTL_CCGR0, offsetof(struct clkctl, ccgr0));
93 DEFINE(CLKCTL_CCGR1, offsetof(struct clkctl, ccgr1));
94 DEFINE(CLKCTL_CCGR2, offsetof(struct clkctl, ccgr2));
95 DEFINE(CLKCTL_CCGR3, offsetof(struct clkctl, ccgr3));
96 DEFINE(CLKCTL_CCGR4, offsetof(struct clkctl, ccgr4));
97 DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
98 DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
99 DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
100#if defined(CONFIG_MX53)
101 DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
102#endif
103
104 /* DPLL */
105 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
106 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
107 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
108 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
109 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
110 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
111 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
112 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
113#endif
114
Masahiro Yamadac54bcf62017-04-14 11:10:23 +0900[diff] [blame]115#ifdef CONFIG_ARM_SMCCC
116 DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
117 DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
118 DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
119 DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
120#endif
121
Masahiro Yamada254d68b2014-03-18 16:38:13 +0900[diff] [blame]122 return 0;
123}