blob: 13e9c64387ed30d3899ff7ff9d1677ad61c555b1 [file] [log] [blame]
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +09001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2016-2017 Socionext Inc.
4 */
5#ifndef __CONFIG_H
6#define __CONFIG_H
7
8/* Timers for fasp(TIMCLK) */
9#define CONFIG_SYS_HZ 1000 /* 1 msec */
10#define CONFIG_SYS_TIMERBASE 0x31080000 /* AP Timer 1 (ARM-SP804) */
11
12/*
13 * SDRAM (for initialize)
14 */
15#define CONFIG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
16#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
17
18#define CONFIG_VERY_BIG_RAM /* SynQuacer supports up to 64GB */
19#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
20
21#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */
22
23/*
24 * Boot info
25 */
26#define CONFIG_SYS_INIT_SP_ADDR (0xe0000000) /* stack of init proccess */
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090027
28/*
29 * Hardware drivers support
30 */
31
32/* RTC */
33#define CONFIG_SYS_I2C_RTC_ADDR 0x51
34
35/* Serial (pl011) */
36#define UART_CLK (62500000)
37#define CONFIG_SERIAL_MULTI
38#define CONFIG_PL011_SERIAL
39#define CONFIG_PL011_CLOCK UART_CLK
40#define CONFIG_PL01x_PORTS {(void *)(0x2a400000)}
41
42#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
43
44/* Support MTD */
45#define CONFIG_SYS_MAX_FLASH_BANKS 1
46#define CONFIG_SYS_FLASH_BASE (0x08000000)
47#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
48
49#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (512 * 1024))
50#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE)
51
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090052#define CONFIG_SYS_CBSIZE 1024
53#define CONFIG_SYS_MAXARGS 128
54#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
55
56/* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */
57/* #define CONFIG_SYS_PCI_64BIT 1 */
58
Masami Hiramatsu3a373862021-06-04 18:45:31 +090059#define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \
Masami Hiramatsu59bd18d2021-07-12 19:36:12 +090060 "mtd mx66u51235f=u-boot.bin raw 200000 100000;" \
Masami Hiramatsu3a373862021-06-04 18:45:31 +090061 "fip.bin raw 180000 78000;" \
62 "optee.bin raw 500000 100000\0"
63
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +090064/* Distro boot settings */
65#ifndef CONFIG_SPL_BUILD
66#ifdef CONFIG_CMD_USB
67#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0)
68#else
69#define BOOT_TARGET_DEVICE_USB(func)
70#endif
71
72#ifdef CONFIG_CMD_MMC
73#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0)
74#else
75#define BOOT_TARGET_DEVICE_MMC(func)
76#endif
77
78#ifdef CONFIG_CMD_NVME
79#define BOOT_TARGET_DEVICE_NVME(func) func(NVME, nvme, 0)
80#else
81#define BOOT_TARGET_DEVICE_NVME(func)
82#endif
83
84#ifdef CONFIG_CMD_SCSI
85#define BOOT_TARGET_DEVICE_SCSI(func) func(SCSI, scsi, 0) func(SCSI, scsi, 1)
86#else
87#define BOOT_TARGET_DEVICE_SCSI(func)
88#endif
89
90#define BOOT_TARGET_DEVICES(func) \
91 BOOT_TARGET_DEVICE_USB(func) \
92 BOOT_TARGET_DEVICE_MMC(func) \
93 BOOT_TARGET_DEVICE_SCSI(func) \
94 BOOT_TARGET_DEVICE_NVME(func) \
95
96#include <config_distro_bootcmd.h>
97#else /* CONFIG_SPL_BUILD */
98#define BOOTENV
99#endif
100
101#define CONFIG_EXTRA_ENV_SETTINGS \
102 "fdt_addr_r=0x9fe00000\0" \
103 "kernel_addr_r=0x90000000\0" \
104 "ramdisk_addr_r=0xa0000000\0" \
105 "scriptaddr=0x88000000\0" \
106 "pxefile_addr_r=0x88100000\0" \
Masami Hiramatsu3a373862021-06-04 18:45:31 +0900107 DEFAULT_DFU_ALT_INFO \
Masami Hiramatsu5cd4a352021-06-04 18:45:10 +0900108 BOOTENV
109
110#endif /* __CONFIG_H */