blob: 5fe30723c243e0d7c8664c26c90cf8b5debce21e [file] [log] [blame]
Simon Glassff3e0772015-03-05 12:25:25 -07001/*
2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <fdtdec.h>
12#include <inttypes.h>
13#include <pci.h>
14#include <dm/lists.h>
15#include <dm/root.h>
16#include <dm/device-internal.h>
Bin Meng348b7442015-08-20 06:40:23 -070017#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18#include <asm/fsp/fsp_support.h>
19#endif
Simon Glassff3e0772015-03-05 12:25:25 -070020
21DECLARE_GLOBAL_DATA_PTR;
22
Simon Glass983c6ba22015-08-31 18:55:35 -060023static int pci_get_bus(int busnum, struct udevice **busp)
24{
25 int ret;
26
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
28
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
30 if (ret == -ENODEV) {
31 ret = uclass_first_device(UCLASS_PCI, busp);
32 if (ret)
33 return ret;
34 else if (!*busp)
35 return -ENODEV;
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
37 }
38
39 return ret;
40}
41
Simon Glassff3e0772015-03-05 12:25:25 -070042struct pci_controller *pci_bus_to_hose(int busnum)
43{
44 struct udevice *bus;
45 int ret;
46
Simon Glass983c6ba22015-08-31 18:55:35 -060047 ret = pci_get_bus(busnum, &bus);
Simon Glassff3e0772015-03-05 12:25:25 -070048 if (ret) {
49 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
50 return NULL;
51 }
Simon Glass983c6ba22015-08-31 18:55:35 -060052
Simon Glassff3e0772015-03-05 12:25:25 -070053 return dev_get_uclass_priv(bus);
54}
55
Simon Glass9f60fb02015-11-19 20:27:00 -070056struct udevice *pci_get_controller(struct udevice *dev)
57{
58 while (device_is_on_pci_bus(dev))
59 dev = dev->parent;
60
61 return dev;
62}
63
Simon Glass4b515e42015-07-06 16:47:46 -060064pci_dev_t pci_get_bdf(struct udevice *dev)
65{
66 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
67 struct udevice *bus = dev->parent;
68
69 return PCI_ADD_BUS(bus->seq, pplat->devfn);
70}
71
Simon Glassff3e0772015-03-05 12:25:25 -070072/**
73 * pci_get_bus_max() - returns the bus number of the last active bus
74 *
75 * @return last bus number, or -1 if no active buses
76 */
77static int pci_get_bus_max(void)
78{
79 struct udevice *bus;
80 struct uclass *uc;
81 int ret = -1;
82
83 ret = uclass_get(UCLASS_PCI, &uc);
84 uclass_foreach_dev(bus, uc) {
85 if (bus->seq > ret)
86 ret = bus->seq;
87 }
88
89 debug("%s: ret=%d\n", __func__, ret);
90
91 return ret;
92}
93
94int pci_last_busno(void)
95{
Bin Meng069155c2015-10-01 00:36:01 -070096 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070097}
98
99int pci_get_ff(enum pci_size_t size)
100{
101 switch (size) {
102 case PCI_SIZE_8:
103 return 0xff;
104 case PCI_SIZE_16:
105 return 0xffff;
106 default:
107 return 0xffffffff;
108 }
109}
110
111int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
112 struct udevice **devp)
113{
114 struct udevice *dev;
115
116 for (device_find_first_child(bus, &dev);
117 dev;
118 device_find_next_child(&dev)) {
119 struct pci_child_platdata *pplat;
120
121 pplat = dev_get_parent_platdata(dev);
122 if (pplat && pplat->devfn == find_devfn) {
123 *devp = dev;
124 return 0;
125 }
126 }
127
128 return -ENODEV;
129}
130
131int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
132{
133 struct udevice *bus;
134 int ret;
135
Simon Glass983c6ba22015-08-31 18:55:35 -0600136 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700137 if (ret)
138 return ret;
139 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
140}
141
142static int pci_device_matches_ids(struct udevice *dev,
143 struct pci_device_id *ids)
144{
145 struct pci_child_platdata *pplat;
146 int i;
147
148 pplat = dev_get_parent_platdata(dev);
149 if (!pplat)
150 return -EINVAL;
151 for (i = 0; ids[i].vendor != 0; i++) {
152 if (pplat->vendor == ids[i].vendor &&
153 pplat->device == ids[i].device)
154 return i;
155 }
156
157 return -EINVAL;
158}
159
160int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
161 int *indexp, struct udevice **devp)
162{
163 struct udevice *dev;
164
165 /* Scan all devices on this bus */
166 for (device_find_first_child(bus, &dev);
167 dev;
168 device_find_next_child(&dev)) {
169 if (pci_device_matches_ids(dev, ids) >= 0) {
170 if ((*indexp)-- <= 0) {
171 *devp = dev;
172 return 0;
173 }
174 }
175 }
176
177 return -ENODEV;
178}
179
180int pci_find_device_id(struct pci_device_id *ids, int index,
181 struct udevice **devp)
182{
183 struct udevice *bus;
184
185 /* Scan all known buses */
186 for (uclass_first_device(UCLASS_PCI, &bus);
187 bus;
188 uclass_next_device(&bus)) {
189 if (!pci_bus_find_devices(bus, ids, &index, devp))
190 return 0;
191 }
192 *devp = NULL;
193
194 return -ENODEV;
195}
196
197int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
198 unsigned long value, enum pci_size_t size)
199{
200 struct dm_pci_ops *ops;
201
202 ops = pci_get_ops(bus);
203 if (!ops->write_config)
204 return -ENOSYS;
205 return ops->write_config(bus, bdf, offset, value, size);
206}
207
208int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
209 enum pci_size_t size)
210{
211 struct udevice *bus;
212 int ret;
213
Simon Glass983c6ba22015-08-31 18:55:35 -0600214 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700215 if (ret)
216 return ret;
217
Bin Meng4d8615c2015-07-19 00:20:04 +0800218 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700219}
220
Simon Glass66afb4e2015-08-10 07:05:03 -0600221int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
222 enum pci_size_t size)
223{
224 struct udevice *bus;
225
Bin Meng1e0f2262015-09-11 03:24:34 -0700226 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600227 bus = bus->parent;
228 return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
229}
230
231
Simon Glassff3e0772015-03-05 12:25:25 -0700232int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
233{
234 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
235}
236
237int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
238{
239 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
240}
241
242int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
243{
244 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
245}
246
Simon Glass66afb4e2015-08-10 07:05:03 -0600247int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
248{
249 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
250}
251
252int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
253{
254 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
255}
256
257int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
258{
259 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
260}
261
Simon Glassff3e0772015-03-05 12:25:25 -0700262int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
263 unsigned long *valuep, enum pci_size_t size)
264{
265 struct dm_pci_ops *ops;
266
267 ops = pci_get_ops(bus);
268 if (!ops->read_config)
269 return -ENOSYS;
270 return ops->read_config(bus, bdf, offset, valuep, size);
271}
272
273int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
274 enum pci_size_t size)
275{
276 struct udevice *bus;
277 int ret;
278
Simon Glass983c6ba22015-08-31 18:55:35 -0600279 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700280 if (ret)
281 return ret;
282
Bin Meng4d8615c2015-07-19 00:20:04 +0800283 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700284}
285
Simon Glass66afb4e2015-08-10 07:05:03 -0600286int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
287 enum pci_size_t size)
288{
289 struct udevice *bus;
290
Bin Meng1e0f2262015-09-11 03:24:34 -0700291 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600292 bus = bus->parent;
293 return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
294 size);
295}
296
Simon Glassff3e0772015-03-05 12:25:25 -0700297int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
298{
299 unsigned long value;
300 int ret;
301
302 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
303 if (ret)
304 return ret;
305 *valuep = value;
306
307 return 0;
308}
309
310int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
311{
312 unsigned long value;
313 int ret;
314
315 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
316 if (ret)
317 return ret;
318 *valuep = value;
319
320 return 0;
321}
322
323int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
324{
325 unsigned long value;
326 int ret;
327
328 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
329 if (ret)
330 return ret;
331 *valuep = value;
332
333 return 0;
334}
335
Simon Glass66afb4e2015-08-10 07:05:03 -0600336int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
337{
338 unsigned long value;
339 int ret;
340
341 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
342 if (ret)
343 return ret;
344 *valuep = value;
345
346 return 0;
347}
348
349int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
350{
351 unsigned long value;
352 int ret;
353
354 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
355 if (ret)
356 return ret;
357 *valuep = value;
358
359 return 0;
360}
361
362int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
363{
364 unsigned long value;
365 int ret;
366
367 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
368 if (ret)
369 return ret;
370 *valuep = value;
371
372 return 0;
373}
374
Bin Mengbbbcb522015-10-01 00:36:02 -0700375static void set_vga_bridge_bits(struct udevice *dev)
376{
377 struct udevice *parent = dev->parent;
378 u16 bc;
379
380 while (parent->seq != 0) {
381 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
382 bc |= PCI_BRIDGE_CTL_VGA;
383 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
384 parent = parent->parent;
385 }
386}
387
Simon Glassff3e0772015-03-05 12:25:25 -0700388int pci_auto_config_devices(struct udevice *bus)
389{
390 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700391 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700392 unsigned int sub_bus;
393 struct udevice *dev;
394 int ret;
395
396 sub_bus = bus->seq;
397 debug("%s: start\n", __func__);
398 pciauto_config_init(hose);
399 for (ret = device_find_first_child(bus, &dev);
400 !ret && dev;
401 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700402 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600403 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700404
Simon Glassff3e0772015-03-05 12:25:25 -0700405 debug("%s: device %s\n", __func__, dev->name);
Simon Glass4d214552015-09-08 17:52:47 -0600406 ret = pciauto_config_device(hose, pci_get_bdf(dev));
407 if (ret < 0)
408 return ret;
409 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700410 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700411
412 pplat = dev_get_parent_platdata(dev);
413 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
414 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700415 }
416 debug("%s: done\n", __func__);
417
418 return sub_bus;
419}
420
421int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
422{
423 struct udevice *parent, *bus;
424 int sub_bus;
425 int ret;
426
427 debug("%s\n", __func__);
428 parent = hose->bus;
429
430 /* Find the bus within the parent */
Bin Meng8326f132015-07-19 00:20:05 +0800431 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700432 if (ret) {
433 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
434 bdf, parent->name, ret);
435 return ret;
436 }
437
438 sub_bus = pci_get_bus_max() + 1;
439 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5afeb4b2015-06-07 08:50:41 -0600440 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700441
442 ret = device_probe(bus);
443 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600444 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700445 ret);
446 return ret;
447 }
448 if (sub_bus != bus->seq) {
449 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
450 __func__, bus->name, bus->seq, sub_bus);
451 return -EPIPE;
452 }
453 sub_bus = pci_get_bus_max();
454 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
455
456 return sub_bus;
457}
458
Simon Glassaba92962015-07-06 16:47:44 -0600459/**
460 * pci_match_one_device - Tell if a PCI device structure has a matching
461 * PCI device id structure
462 * @id: single PCI device id structure to match
463 * @dev: the PCI device structure to match against
464 *
465 * Returns the matching pci_device_id structure or %NULL if there is no match.
466 */
467static bool pci_match_one_id(const struct pci_device_id *id,
468 const struct pci_device_id *find)
469{
470 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
471 (id->device == PCI_ANY_ID || id->device == find->device) &&
472 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
473 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
474 !((id->class ^ find->class) & id->class_mask))
475 return true;
476
477 return false;
478}
479
480/**
481 * pci_find_and_bind_driver() - Find and bind the right PCI driver
482 *
483 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600484 *
485 * @parent: Parent bus
486 * @find_id: Specification of the driver to find
487 * @bdf: Bus/device/function addreess - see PCI_BDF()
488 * @devp: Returns a pointer to the device created
489 * @return 0 if OK, -EPERM if the device is not needed before relocation and
490 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600491 */
492static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600493 struct pci_device_id *find_id,
494 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600495{
496 struct pci_driver_entry *start, *entry;
497 const char *drv;
498 int n_ents;
499 int ret;
500 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700501 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600502
503 *devp = NULL;
504
505 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
506 find_id->vendor, find_id->device);
507 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
508 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
509 for (entry = start; entry != start + n_ents; entry++) {
510 const struct pci_device_id *id;
511 struct udevice *dev;
512 const struct driver *drv;
513
514 for (id = entry->match;
515 id->vendor || id->subvendor || id->class_mask;
516 id++) {
517 if (!pci_match_one_id(id, find_id))
518 continue;
519
520 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700521
522 /*
523 * In the pre-relocation phase, we only bind devices
524 * whose driver has the DM_FLAG_PRE_RELOC set, to save
525 * precious memory space as on some platforms as that
526 * space is pretty limited (ie: using Cache As RAM).
527 */
528 if (!(gd->flags & GD_FLG_RELOC) &&
529 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600530 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700531
Simon Glassaba92962015-07-06 16:47:44 -0600532 /*
533 * We could pass the descriptor to the driver as
534 * platdata (instead of NULL) and allow its bind()
535 * method to return -ENOENT if it doesn't support this
536 * device. That way we could continue the search to
537 * find another driver. For now this doesn't seem
538 * necesssary, so just bind the first match.
539 */
540 ret = device_bind(parent, drv, drv->name, NULL, -1,
541 &dev);
542 if (ret)
543 goto error;
544 debug("%s: Match found: %s\n", __func__, drv->name);
545 dev->driver_data = find_id->driver_data;
546 *devp = dev;
547 return 0;
548 }
549 }
550
Bin Meng08fc7b82015-08-20 06:40:17 -0700551 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
552 /*
553 * In the pre-relocation phase, we only bind bridge devices to save
554 * precious memory space as on some platforms as that space is pretty
555 * limited (ie: using Cache As RAM).
556 */
557 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600558 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700559
Simon Glassaba92962015-07-06 16:47:44 -0600560 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800561 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
562 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600563 str = strdup(name);
564 if (!str)
565 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700566 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
567
Simon Glassaba92962015-07-06 16:47:44 -0600568 ret = device_bind_driver(parent, drv, str, devp);
569 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600570 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
Simon Glassaba92962015-07-06 16:47:44 -0600571 return ret;
572 }
573 debug("%s: No match found: bound generic driver instead\n", __func__);
574
575 return 0;
576
577error:
578 debug("%s: No match found: error %d\n", __func__, ret);
579 return ret;
580}
581
Simon Glassff3e0772015-03-05 12:25:25 -0700582int pci_bind_bus_devices(struct udevice *bus)
583{
584 ulong vendor, device;
585 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800586 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700587 bool found_multi;
588 int ret;
589
590 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800591 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
592 PCI_MAX_PCI_FUNCTIONS - 1);
593 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
594 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700595 struct pci_child_platdata *pplat;
596 struct udevice *dev;
597 ulong class;
598
Bin Meng4d8615c2015-07-19 00:20:04 +0800599 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700600 continue;
601 /* Check only the first access, we don't expect problems */
Bin Meng4d8615c2015-07-19 00:20:04 +0800602 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassff3e0772015-03-05 12:25:25 -0700603 &header_type, PCI_SIZE_8);
604 if (ret)
605 goto error;
Bin Meng4d8615c2015-07-19 00:20:04 +0800606 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassff3e0772015-03-05 12:25:25 -0700607 PCI_SIZE_16);
608 if (vendor == 0xffff || vendor == 0x0000)
609 continue;
610
Bin Meng4d8615c2015-07-19 00:20:04 +0800611 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700612 found_multi = header_type & 0x80;
613
614 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800615 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
616 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700617 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800618 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600619 PCI_SIZE_32);
620 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700621
622 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800623 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700624
Simon Glassaba92962015-07-06 16:47:44 -0600625 /* Search for a driver */
626
Simon Glassff3e0772015-03-05 12:25:25 -0700627 /* If nothing in the device tree, bind a generic device */
628 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600629 struct pci_device_id find_id;
630 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700631
Simon Glassaba92962015-07-06 16:47:44 -0600632 memset(&find_id, '\0', sizeof(find_id));
633 find_id.vendor = vendor;
634 find_id.device = device;
635 find_id.class = class;
636 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800637 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600638 PCI_SUBSYSTEM_VENDOR_ID,
639 &val, PCI_SIZE_32);
640 find_id.subvendor = val & 0xffff;
641 find_id.subdevice = val >> 16;
642 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800643 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600644 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700645 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600646 if (ret == -EPERM)
647 continue;
648 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700649 return ret;
650
651 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600652 pplat = dev_get_parent_platdata(dev);
653 pplat->devfn = PCI_MASK_BUS(bdf);
654 pplat->vendor = vendor;
655 pplat->device = device;
656 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700657 }
658
659 return 0;
660error:
661 printf("Cannot read bus configuration: %d\n", ret);
662
663 return ret;
664}
665
666static int pci_uclass_post_bind(struct udevice *bus)
667{
668 /*
Bin Meng1887ed32015-08-24 01:14:01 -0700669 * If there is no pci device listed in the device tree,
670 * don't bother scanning the device tree.
671 */
672 if (bus->of_offset == -1)
673 return 0;
674
675 /*
Simon Glassff3e0772015-03-05 12:25:25 -0700676 * Scan the device tree for devices. This does not probe the PCI bus,
677 * as this is not permitted while binding. It just finds devices
678 * mentioned in the device tree.
679 *
680 * Before relocation, only bind devices marked for pre-relocation
681 * use.
682 */
683 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
684 gd->flags & GD_FLG_RELOC ? false : true);
685}
686
687static int decode_regions(struct pci_controller *hose, const void *blob,
688 int parent_node, int node)
689{
690 int pci_addr_cells, addr_cells, size_cells;
Simon Glass2084c5a2015-11-19 20:26:57 -0700691 phys_addr_t base = 0, size;
Simon Glassff3e0772015-03-05 12:25:25 -0700692 int cells_per_record;
693 const u32 *prop;
694 int len;
695 int i;
696
697 prop = fdt_getprop(blob, node, "ranges", &len);
698 if (!prop)
699 return -EINVAL;
700 pci_addr_cells = fdt_address_cells(blob, node);
701 addr_cells = fdt_address_cells(blob, parent_node);
702 size_cells = fdt_size_cells(blob, node);
703
704 /* PCI addresses are always 3-cells */
705 len /= sizeof(u32);
706 cells_per_record = pci_addr_cells + addr_cells + size_cells;
707 hose->region_count = 0;
708 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
709 cells_per_record);
710 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
711 u64 pci_addr, addr, size;
712 int space_code;
713 u32 flags;
714 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700715 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700716
717 if (len < cells_per_record)
718 break;
719 flags = fdt32_to_cpu(prop[0]);
720 space_code = (flags >> 24) & 3;
721 pci_addr = fdtdec_get_number(prop + 1, 2);
722 prop += pci_addr_cells;
723 addr = fdtdec_get_number(prop, addr_cells);
724 prop += addr_cells;
725 size = fdtdec_get_number(prop, size_cells);
726 prop += size_cells;
727 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
728 ", size=%" PRIx64 ", space_code=%d\n", __func__,
729 hose->region_count, pci_addr, addr, size, space_code);
730 if (space_code & 2) {
731 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
732 PCI_REGION_MEM;
733 } else if (space_code & 1) {
734 type = PCI_REGION_IO;
735 } else {
736 continue;
737 }
Simon Glass9526d832015-11-19 20:26:58 -0700738 pos = -1;
739 for (i = 0; i < hose->region_count; i++) {
740 if (hose->regions[i].flags == type)
741 pos = i;
742 }
743 if (pos == -1)
744 pos = hose->region_count++;
745 debug(" - type=%d, pos=%d\n", type, pos);
746 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700747 }
748
749 /* Add a region for our local memory */
Simon Glass2084c5a2015-11-19 20:26:57 -0700750 size = gd->ram_size;
751#ifdef CONFIG_SYS_SDRAM_BASE
752 base = CONFIG_SYS_SDRAM_BASE;
753#endif
754 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
755 size = gd->pci_ram_top - base;
756 pci_set_region(hose->regions + hose->region_count++, base, base,
757 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Simon Glassff3e0772015-03-05 12:25:25 -0700758
759 return 0;
760}
761
762static int pci_uclass_pre_probe(struct udevice *bus)
763{
764 struct pci_controller *hose;
765 int ret;
766
767 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
768 bus->parent->name);
769 hose = bus->uclass_priv;
770
771 /* For bridges, use the top-level PCI controller */
772 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
773 hose->ctlr = bus;
774 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
775 bus->of_offset);
776 if (ret) {
777 debug("%s: Cannot decode regions\n", __func__);
778 return ret;
779 }
780 } else {
781 struct pci_controller *parent_hose;
782
783 parent_hose = dev_get_uclass_priv(bus->parent);
784 hose->ctlr = parent_hose->bus;
785 }
786 hose->bus = bus;
787 hose->first_busno = bus->seq;
788 hose->last_busno = bus->seq;
789
790 return 0;
791}
792
793static int pci_uclass_post_probe(struct udevice *bus)
794{
795 int ret;
796
Simon Glassff3e0772015-03-05 12:25:25 -0700797 debug("%s: probing bus %d\n", __func__, bus->seq);
798 ret = pci_bind_bus_devices(bus);
799 if (ret)
800 return ret;
801
802#ifdef CONFIG_PCI_PNP
803 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600804 if (ret < 0)
805 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700806#endif
807
Bin Meng348b7442015-08-20 06:40:23 -0700808#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
809 /*
810 * Per Intel FSP specification, we should call FSP notify API to
811 * inform FSP that PCI enumeration has been done so that FSP will
812 * do any necessary initialization as required by the chipset's
813 * BIOS Writer's Guide (BWG).
814 *
815 * Unfortunately we have to put this call here as with driver model,
816 * the enumeration is all done on a lazy basis as needed, so until
817 * something is touched on PCI it won't happen.
818 *
819 * Note we only call this 1) after U-Boot is relocated, and 2)
820 * root bus has finished probing.
821 */
Simon Glass4d214552015-09-08 17:52:47 -0600822 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -0700823 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -0600824 if (ret)
825 return ret;
826 }
Bin Meng348b7442015-08-20 06:40:23 -0700827#endif
828
Simon Glass4d214552015-09-08 17:52:47 -0600829 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -0700830}
831
832static int pci_uclass_child_post_bind(struct udevice *dev)
833{
834 struct pci_child_platdata *pplat;
835 struct fdt_pci_addr addr;
836 int ret;
837
838 if (dev->of_offset == -1)
839 return 0;
840
841 /*
842 * We could read vendor, device, class if available. But for now we
843 * just check the address.
844 */
845 pplat = dev_get_parent_platdata(dev);
846 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
847 FDT_PCI_SPACE_CONFIG, "reg", &addr);
848
849 if (ret) {
850 if (ret != -ENOENT)
851 return -EINVAL;
852 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -0700853 /* extract the devfn from fdt_pci_addr */
854 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -0700855 }
856
857 return 0;
858}
859
Bin Meng4d8615c2015-07-19 00:20:04 +0800860static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
861 uint offset, ulong *valuep,
862 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -0700863{
864 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -0700865
866 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
867}
868
Bin Meng4d8615c2015-07-19 00:20:04 +0800869static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
870 uint offset, ulong value,
871 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -0700872{
873 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -0700874
875 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
876}
877
Simon Glass76c3fbc2015-08-10 07:05:04 -0600878static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
879{
880 struct udevice *dev;
881 int ret = 0;
882
883 /*
884 * Scan through all the PCI controllers. On x86 there will only be one
885 * but that is not necessarily true on other hardware.
886 */
887 do {
888 device_find_first_child(bus, &dev);
889 if (dev) {
890 *devp = dev;
891 return 0;
892 }
893 ret = uclass_next_device(&bus);
894 if (ret)
895 return ret;
896 } while (bus);
897
898 return 0;
899}
900
901int pci_find_next_device(struct udevice **devp)
902{
903 struct udevice *child = *devp;
904 struct udevice *bus = child->parent;
905 int ret;
906
907 /* First try all the siblings */
908 *devp = NULL;
909 while (child) {
910 device_find_next_child(&child);
911 if (child) {
912 *devp = child;
913 return 0;
914 }
915 }
916
917 /* We ran out of siblings. Try the next bus */
918 ret = uclass_next_device(&bus);
919 if (ret)
920 return ret;
921
922 return bus ? skip_to_next_device(bus, devp) : 0;
923}
924
925int pci_find_first_device(struct udevice **devp)
926{
927 struct udevice *bus;
928 int ret;
929
930 *devp = NULL;
931 ret = uclass_first_device(UCLASS_PCI, &bus);
932 if (ret)
933 return ret;
934
935 return skip_to_next_device(bus, devp);
936}
937
Simon Glass9289db62015-11-19 20:26:59 -0700938ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
939{
940 switch (size) {
941 case PCI_SIZE_8:
942 return (value >> ((offset & 3) * 8)) & 0xff;
943 case PCI_SIZE_16:
944 return (value >> ((offset & 2) * 8)) & 0xffff;
945 default:
946 return value;
947 }
948}
949
950ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
951 enum pci_size_t size)
952{
953 uint off_mask;
954 uint val_mask, shift;
955 ulong ldata, mask;
956
957 switch (size) {
958 case PCI_SIZE_8:
959 off_mask = 3;
960 val_mask = 0xff;
961 break;
962 case PCI_SIZE_16:
963 off_mask = 2;
964 val_mask = 0xffff;
965 break;
966 default:
967 return value;
968 }
969 shift = (offset & off_mask) * 8;
970 ldata = (value & val_mask) << shift;
971 mask = val_mask << shift;
972 value = (old & ~mask) | ldata;
973
974 return value;
975}
976
Simon Glassf9260332015-11-19 20:27:01 -0700977int pci_get_regions(struct udevice *dev, struct pci_region **iop,
978 struct pci_region **memp, struct pci_region **prefp)
979{
980 struct udevice *bus = pci_get_controller(dev);
981 struct pci_controller *hose = dev_get_uclass_priv(bus);
982 int i;
983
984 *iop = NULL;
985 *memp = NULL;
986 *prefp = NULL;
987 for (i = 0; i < hose->region_count; i++) {
988 switch (hose->regions[i].flags) {
989 case PCI_REGION_IO:
990 if (!*iop || (*iop)->size < hose->regions[i].size)
991 *iop = hose->regions + i;
992 break;
993 case PCI_REGION_MEM:
994 if (!*memp || (*memp)->size < hose->regions[i].size)
995 *memp = hose->regions + i;
996 break;
997 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
998 if (!*prefp || (*prefp)->size < hose->regions[i].size)
999 *prefp = hose->regions + i;
1000 break;
1001 }
1002 }
1003
1004 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1005}
1006
Simon Glassff3e0772015-03-05 12:25:25 -07001007UCLASS_DRIVER(pci) = {
1008 .id = UCLASS_PCI,
1009 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001010 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glassff3e0772015-03-05 12:25:25 -07001011 .post_bind = pci_uclass_post_bind,
1012 .pre_probe = pci_uclass_pre_probe,
1013 .post_probe = pci_uclass_post_probe,
1014 .child_post_bind = pci_uclass_child_post_bind,
1015 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1016 .per_child_platdata_auto_alloc_size =
1017 sizeof(struct pci_child_platdata),
1018};
1019
1020static const struct dm_pci_ops pci_bridge_ops = {
1021 .read_config = pci_bridge_read_config,
1022 .write_config = pci_bridge_write_config,
1023};
1024
1025static const struct udevice_id pci_bridge_ids[] = {
1026 { .compatible = "pci-bridge" },
1027 { }
1028};
1029
1030U_BOOT_DRIVER(pci_bridge_drv) = {
1031 .name = "pci_bridge_drv",
1032 .id = UCLASS_PCI,
1033 .of_match = pci_bridge_ids,
1034 .ops = &pci_bridge_ops,
1035};
1036
1037UCLASS_DRIVER(pci_generic) = {
1038 .id = UCLASS_PCI_GENERIC,
1039 .name = "pci_generic",
1040};
1041
1042static const struct udevice_id pci_generic_ids[] = {
1043 { .compatible = "pci-generic" },
1044 { }
1045};
1046
1047U_BOOT_DRIVER(pci_generic_drv) = {
1048 .name = "pci_generic_drv",
1049 .id = UCLASS_PCI_GENERIC,
1050 .of_match = pci_generic_ids,
1051};