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Alison Wang186fc4d2012-10-18 19:25:52 +00001/*
2 * Configuation settings for the Freescale MCF54418 TWR board.
3 *
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Alison Wang186fc4d2012-10-18 19:25:52 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M54418TWR_H
15#define _M54418TWR_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
Alison Wang186fc4d2012-10-18 19:25:52 +000021#define CONFIG_M54418TWR /* M54418TWR board */
22
23#define CONFIG_MCFUART
24#define CONFIG_SYS_UART_PORT (0)
25#define CONFIG_BAUDRATE 115200
26#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
27
28#undef CONFIG_WATCHDOG
29
30#define CONFIG_TIMESTAMP /* Print image info with timestamp */
31
32/*
33 * BOOTP options
34 */
35#define CONFIG_BOOTP_BOOTFILESIZE
36#define CONFIG_BOOTP_BOOTPATH
37#define CONFIG_BOOTP_GATEWAY
38#define CONFIG_BOOTP_HOSTNAME
39
40/* Command line configuration */
Alison Wang186fc4d2012-10-18 19:25:52 +000041#define CONFIG_CMD_CACHE
42#undef CONFIG_CMD_DATE
43#define CONFIG_CMD_DHCP
Alison Wang186fc4d2012-10-18 19:25:52 +000044#undef CONFIG_CMD_I2C
45#undef CONFIG_CMD_JFFS2
46#undef CONFIG_CMD_UBI
Alison Wang186fc4d2012-10-18 19:25:52 +000047#define CONFIG_CMD_MII
48#undef CONFIG_CMD_NAND
Alison Wang186fc4d2012-10-18 19:25:52 +000049#define CONFIG_CMD_PING
50#define CONFIG_CMD_REGINFO
51#define CONFIG_CMD_SPI
52#define CONFIG_CMD_SF
Alison Wang186fc4d2012-10-18 19:25:52 +000053
Alison Wang186fc4d2012-10-18 19:25:52 +000054
55/*
56 * NAND FLASH
57 */
58#ifdef CONFIG_CMD_NAND
59#define CONFIG_JFFS2_NAND
60#define CONFIG_NAND_FSL_NFC
61#define CONFIG_SYS_NAND_BASE 0xFC0FC000
62#define CONFIG_SYS_MAX_NAND_DEVICE 1
63#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
64#define CONFIG_SYS_NAND_SELECT_DEVICE
Alison Wang186fc4d2012-10-18 19:25:52 +000065#endif
66
67/* Network configuration */
68#define CONFIG_MCFFEC
69#ifdef CONFIG_MCFFEC
Alison Wang186fc4d2012-10-18 19:25:52 +000070#define CONFIG_MII 1
71#define CONFIG_MII_INIT 1
72#define CONFIG_SYS_DISCOVER_PHY
73#define CONFIG_SYS_RX_ETH_BUFFER 2
74#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
75#define CONFIG_SYS_TX_ETH_BUFFER 2
76#define CONFIG_HAS_ETH1
77
78#define CONFIG_SYS_FEC0_PINMUX 0
79#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
80#define CONFIG_SYS_FEC1_PINMUX 0
81#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
82#define MCFFEC_TOUT_LOOP 50000
83#define CONFIG_SYS_FEC0_PHYADDR 0
84#define CONFIG_SYS_FEC1_PHYADDR 1
85
86#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
87
88#ifdef CONFIG_SYS_NAND_BOOT
89#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
90 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
91 "-(jffs2) console=ttyS0,115200"
92#else
93#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
94 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
95 __stringify(CONFIG_IPADDR) " ip=" \
96 __stringify(CONFIG_IPADDR) ":" \
97 __stringify(CONFIG_SERVERIP)":" \
98 __stringify(CONFIG_GATEWAYIP)": " \
99 __stringify(CONFIG_NETMASK) \
100 "::eth0:off:rw console=ttyS0,115200"
101#endif
102
Alison Wang186fc4d2012-10-18 19:25:52 +0000103#define CONFIG_ETHPRIME "FEC0"
104#define CONFIG_IPADDR 192.168.1.2
105#define CONFIG_NETMASK 255.255.255.0
106#define CONFIG_SERVERIP 192.168.1.1
107#define CONFIG_GATEWAYIP 192.168.1.1
108
Alison Wang186fc4d2012-10-18 19:25:52 +0000109#define CONFIG_SYS_FEC_BUF_USE_SRAM
110/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
111#ifndef CONFIG_SYS_DISCOVER_PHY
112#define FECDUPLEX FULL
113#define FECSPEED _100BASET
114#define LINKSTATUS 1
115#else
116#define LINKSTATUS 0
117#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
118#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
119#endif
120#endif /* CONFIG_SYS_DISCOVER_PHY */
121#endif
122
123#define CONFIG_HOSTNAME M54418TWR
124
125#if defined(CONFIG_CF_SBF)
126/* ST Micro serial flash */
127#define CONFIG_SYS_LOAD_ADDR2 0x40010007
128#define CONFIG_EXTRA_ENV_SETTINGS \
129 "netdev=eth0\0" \
130 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
131 "loadaddr=0x40010000\0" \
132 "sbfhdr=sbfhdr.bin\0" \
133 "uboot=u-boot.bin\0" \
134 "load=tftp ${loadaddr} ${sbfhdr};" \
135 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
136 "upd=run load; run prog\0" \
137 "prog=sf probe 0:1 1000000 3;" \
138 "sf erase 0 40000;" \
139 "sf write ${loadaddr} 0 40000;" \
140 "save\0" \
141 ""
142#elif defined(CONFIG_SYS_NAND_BOOT)
143#define CONFIG_EXTRA_ENV_SETTINGS \
144 "netdev=eth0\0" \
145 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
146 "loadaddr=0x40010000\0" \
147 "u-boot=u-boot.bin\0" \
148 "load=tftp ${loadaddr} ${u-boot};\0" \
149 "upd=run load; run prog\0" \
150 "prog=nand device 0;" \
151 "nand erase 0 40000;" \
152 "nb_update ${loadaddr} ${filesize};" \
153 "save\0" \
154 ""
155#else
156#define CONFIG_SYS_UBOOT_END 0x3FFFF
157#define CONFIG_EXTRA_ENV_SETTINGS \
158 "netdev=eth0\0" \
159 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
160 "loadaddr=40010000\0" \
161 "u-boot=u-boot.bin\0" \
162 "load=tftp ${loadaddr) ${u-boot}\0" \
163 "upd=run load; run prog\0" \
164 "prog=prot off mram" " ;" \
165 "cp.b ${loadaddr} 0 ${filesize};" \
166 "save\0" \
167 ""
168#endif
169
170/* Realtime clock */
171#undef CONFIG_MCFRTC
172#define CONFIG_RTC_MCFRRTC
173#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
174
175/* Timer */
176#define CONFIG_MCFTMR
177#undef CONFIG_MCFPIT
178
179/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200180#undef CONFIG_SYS_FSL_I2C
Alison Wang186fc4d2012-10-18 19:25:52 +0000181#undef CONFIG_HARD_I2C /* I2C with hardware support */
Heiko Schocherea818db2013-01-29 08:53:15 +0100182#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Alison Wang186fc4d2012-10-18 19:25:52 +0000183/* I2C speed and slave address */
184#define CONFIG_SYS_I2C_SPEED 80000
185#define CONFIG_SYS_I2C_SLAVE 0x7F
186#define CONFIG_SYS_I2C_OFFSET 0x58000
187#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
188
189/* DSPI and Serial Flash */
190#define CONFIG_CF_SPI
191#define CONFIG_CF_DSPI
192#define CONFIG_SERIAL_FLASH
193#define CONFIG_HARD_SPI
194#define CONFIG_SYS_SBFHDR_SIZE 0x7
195#ifdef CONFIG_CMD_SPI
Alison Wang186fc4d2012-10-18 19:25:52 +0000196
197# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
198 DSPI_CTAR_PCSSCK_1CLK | \
199 DSPI_CTAR_PASC(0) | \
200 DSPI_CTAR_PDT(0) | \
201 DSPI_CTAR_CSSCK(0) | \
202 DSPI_CTAR_ASC(0) | \
203 DSPI_CTAR_DT(1))
204# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
205# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
206#endif
207
208/* Input, PCI, Flexbus, and VCO */
209#define CONFIG_EXTRA_CLOCK
210
211#define CONFIG_PRAM 2048 /* 2048 KB */
212
213/* HUSH */
214#define CONFIG_SYS_HUSH_PARSER 1
215#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
216
Alison Wang186fc4d2012-10-18 19:25:52 +0000217#define CONFIG_SYS_LONGHELP /* undef to save memory */
218
219#if defined(CONFIG_CMD_KGDB)
220#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
221#else
222#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
223#endif
224/* Print Buffer Size */
225#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
226 sizeof(CONFIG_SYS_PROMPT) + 16)
227#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
228/* Boot Argument Buffer Size */
229#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
230
231#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
232
Alison Wang186fc4d2012-10-18 19:25:52 +0000233#define CONFIG_SYS_MBAR 0xFC000000
234
235/*
236 * Low Level Configuration Settings
237 * (address mappings, register initial values, etc.)
238 * You should know what you are doing if you make changes here.
239 */
240
241/*-----------------------------------------------------------------------
242 * Definitions for initial stack pointer and data area (in DPRAM)
243 */
244#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
245/* End of used area in internal SRAM */
246#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
247#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Alison Wang186fc4d2012-10-18 19:25:52 +0000248#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900249 GENERATED_GBL_DATA_SIZE) - 32)
Alison Wang186fc4d2012-10-18 19:25:52 +0000250#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
251#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
252
253/*-----------------------------------------------------------------------
254 * Start addresses for the final memory configuration
255 * (Set up by the startup code)
256 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
257 */
258#define CONFIG_SYS_SDRAM_BASE 0x40000000
259#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
260
261#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
262#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
263#define CONFIG_SYS_DRAM_TEST
264
265#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
266#define CONFIG_SERIAL_BOOT
267#endif
268
269#if defined(CONFIG_SERIAL_BOOT)
270#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
271#else
272#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
273#endif
274
275#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
276/* Reserve 256 kB for Monitor */
277#define CONFIG_SYS_MONITOR_LEN (256 << 10)
278/* Reserve 256 kB for malloc() */
279#define CONFIG_SYS_MALLOC_LEN (256 << 10)
280
281/*
282 * For booting Linux, the board info and command line data
283 * have to be in the first 8 MB of memory, since this is
284 * the maximum mapped by the Linux kernel during initialization ??
285 */
286/* Initial Memory map for Linux */
287#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
288 (CONFIG_SYS_SDRAM_SIZE << 20))
289
290/* Configuration for environment
291 * Environment is embedded in u-boot in the second sector of the flash
292 */
293#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
294#define CONFIG_SYS_NO_FLASH
295#define CONFIG_ENV_IS_IN_MRAM 1
296#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
297#define CONFIG_ENV_SIZE 0x1000
298#endif
299
300#if defined(CONFIG_CF_SBF)
301#define CONFIG_SYS_NO_FLASH
302#define CONFIG_ENV_IS_IN_SPI_FLASH 1
303#define CONFIG_ENV_SPI_CS 1
304#define CONFIG_ENV_OFFSET 0x40000
305#define CONFIG_ENV_SIZE 0x2000
306#define CONFIG_ENV_SECT_SIZE 0x10000
307#endif
308#if defined(CONFIG_SYS_NAND_BOOT)
309#define CONFIG_SYS_NO_FLASH
Jason Jinb765fce2012-10-25 15:27:37 +0800310#define CONFIG_ENV_IS_NOWHERE
Alison Wang186fc4d2012-10-18 19:25:52 +0000311#define CONFIG_ENV_OFFSET 0x80000
312#define CONFIG_ENV_SIZE 0x20000
313#define CONFIG_ENV_SECT_SIZE 0x20000
314#endif
315#undef CONFIG_ENV_OVERWRITE
316
317/* FLASH organization */
318#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
319
320#undef CONFIG_SYS_FLASH_CFI
321#ifdef CONFIG_SYS_FLASH_CFI
322
323#define CONFIG_FLASH_CFI_DRIVER 1
324/* Max size that the board might have */
325#define CONFIG_SYS_FLASH_SIZE 0x1000000
326#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
327/* max number of memory banks */
328#define CONFIG_SYS_MAX_FLASH_BANKS 1
329/* max number of sectors on one chip */
330#define CONFIG_SYS_MAX_FLASH_SECT 270
331/* "Real" (hardware) sectors protection */
332#define CONFIG_SYS_FLASH_PROTECTION
333#define CONFIG_SYS_FLASH_CHECKSUM
334#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
335#else
336/* max number of sectors on one chip */
337#define CONFIG_SYS_MAX_FLASH_SECT 270
338/* max number of sectors on one chip */
339#define CONFIG_SYS_MAX_FLASH_BANKS 0
340#endif
341
342/*
343 * This is setting for JFFS2 support in u-boot.
344 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
345 */
346#ifdef CONFIG_CMD_JFFS2
347#define CONFIG_JFFS2_DEV "nand0"
348#define CONFIG_JFFS2_PART_OFFSET (0x800000)
349#define CONFIG_CMD_MTDPARTS
350#define CONFIG_MTD_DEVICE
351#define MTDIDS_DEFAULT "nand0=m54418twr.nand"
352
353#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
354 "7m(kernel)," \
355 "-(rootfs)"
356
357#endif
358
359#ifdef CONFIG_CMD_UBI
360#define CONFIG_CMD_MTDPARTS
361#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
362#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
363#define CONFIG_RBTREE
364#define MTDIDS_DEFAULT "nand0=NAND"
365#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
366 "-(ubi)"
367#endif
368/* Cache Configuration */
369#define CONFIG_SYS_CACHELINE_SIZE 16
370#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
371 CONFIG_SYS_INIT_RAM_SIZE - 8)
372#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
373 CONFIG_SYS_INIT_RAM_SIZE - 4)
374#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
375#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
376#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
377 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
378 CF_ACR_EN | CF_ACR_SM_ALL)
379#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
380 CF_CACR_ICINVA | CF_CACR_EUSP)
381#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
382 CF_CACR_DEC | CF_CACR_DDCM_P | \
383 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
384
385#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
386 CONFIG_SYS_INIT_RAM_SIZE - 12)
387
388/*-----------------------------------------------------------------------
389 * Memory bank definitions
390 */
391/*
392 * CS0 - NOR Flash 16MB
393 * CS1 - Available
394 * CS2 - Available
395 * CS3 - Available
396 * CS4 - Available
397 * CS5 - Available
398 */
399
400 /* Flash */
401#define CONFIG_SYS_CS0_BASE 0x00000000
402#define CONFIG_SYS_CS0_MASK 0x000F0101
403#define CONFIG_SYS_CS0_CTRL 0x00001D60
404
405#endif /* _M54418TWR_H */