blob: 84bb044421ee889d795aa89ace5e260f02b4222f [file] [log] [blame]
Mike Frysinger84a9dda2008-10-12 21:32:52 -04001/*
2 * U-boot - Configuration file for BF518F EZBrd board
3 */
4
5#ifndef __CONFIG_BF518F_EZBRD_H__
6#define __CONFIG_BF518F_EZBRD_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysinger84a9dda2008-10-12 21:32:52 -04009
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf518-0.0
Mike Frysinger84a9dda2008-10-12 21:32:52 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 16
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45/* This board has a 64meg MT48H32M16 */
46#define CONFIG_MEM_ADD_WDTH 10
47#define CONFIG_MEM_SIZE 64
48
49#define CONFIG_EBIU_SDRRC_VAL 0x0096
50#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
51
52#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
53#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
54#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
55
Mike Frysinger912da8d2010-01-08 06:14:13 -050056#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysinger84a9dda2008-10-12 21:32:52 -040057#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
58
59
60/*
61 * Network Settings
62 */
63#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
64#define ADI_CMDS_NETWORK 1
65#define CONFIG_BFIN_MAC
Mike Frysinger0c929422009-05-29 18:00:16 -040066#define CONFIG_BFIN_MAC_PINS \
67 { \
68 P_MII0_ETxD0, \
69 P_MII0_ETxD1, \
70 P_MII0_ETxD2, \
71 P_MII0_ETxD3, \
72 P_MII0_ETxEN, \
73 P_MII0_TxCLK, \
74 P_MII0_PHYINT, \
75 P_MII0_COL, \
76 P_MII0_ERxD0, \
77 P_MII0_ERxD1, \
78 P_MII0_ERxD2, \
79 P_MII0_ERxD3, \
80 P_MII0_ERxDV, \
81 P_MII0_ERxCLK, \
82 P_MII0_CRS, \
83 P_MII0_MDC, \
84 P_MII0_MDIO, \
85 0 }
Mike Frysinger84a9dda2008-10-12 21:32:52 -040086#define CONFIG_NETCONSOLE 1
Mike Frysinger84a9dda2008-10-12 21:32:52 -040087#endif
88#define CONFIG_HOSTNAME bf518f-ezbrd
89#define CONFIG_PHY_ADDR 3
Mike Frysinger84a9dda2008-10-12 21:32:52 -040090
91/*
92 * Flash Settings
93 */
94#define CONFIG_FLASH_CFI_DRIVER
95#define CONFIG_SYS_FLASH_BASE 0x20000000
96#define CONFIG_SYS_FLASH_CFI
97#define CONFIG_SYS_FLASH_PROTECTION
98#define CONFIG_SYS_MAX_FLASH_BANKS 1
99#define CONFIG_SYS_MAX_FLASH_SECT 71
100
101
102/*
103 * SPI Settings
104 */
105#define CONFIG_BFIN_SPI
106#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -0400107#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400108
109
110/*
111 * Env Storage Settings
112 */
113#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
114#define CONFIG_ENV_IS_IN_SPI_FLASH
115#define CONFIG_ENV_OFFSET 0x10000
116#define CONFIG_ENV_SIZE 0x2000
117#define CONFIG_ENV_SECT_SIZE 0x10000
118#else
119#define CONFIG_ENV_IS_IN_FLASH
120#define CONFIG_ENV_OFFSET 0x4000
121#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
122#define CONFIG_ENV_SIZE 0x2000
123#define CONFIG_ENV_SECT_SIZE 0x2000
124#endif
Mike Frysinger76d82182009-07-21 22:17:36 -0400125#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400126
127
128/*
129 * I2C Settings
130 */
Scott Jiangc4697032014-11-13 15:30:55 +0800131#define CONFIG_SYS_I2C
Scott Jiangfea9b692014-11-13 15:30:53 +0800132#define CONFIG_SYS_I2C_ADI
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400133
134
135/*
136 * SDH Settings
137 */
138#if !defined(__ADSPBF512__)
Cliff Caie54c8202009-11-20 08:24:43 +0000139#define CONFIG_GENERIC_MMC
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400140#define CONFIG_MMC
141#define CONFIG_BFIN_SDH
142#endif
143
144
145/*
146 * Misc Settings
147 */
Graf Yangab687902009-05-24 02:34:34 -0400148#define CONFIG_BOARD_EARLY_INIT_F
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400149#define CONFIG_MISC_INIT_R
150#define CONFIG_RTC_BFIN
151#define CONFIG_UART_CONSOLE 0
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400152
153/*
154 * Pull in common ADI header for remaining command/environment setup
155 */
156#include <configs/bfin_adi_common.h>
157
Mike Frysinger84a9dda2008-10-12 21:32:52 -0400158#endif