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Anatolij Gustschin4387cf12012-08-31 01:29:57 +00001/*
2 * Common configuration options for ifm camera boards
3 *
4 * (C) Copyright 2005
5 * Sebastien Cazaux, ifm electronic gmbh
6 *
7 * (C) Copyright 2012
8 * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschin4387cf12012-08-31 01:29:57 +000011 */
12
13#ifndef __O2D_CONFIG_H
14#define __O2D_CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
Anatolij Gustschin4387cf12012-08-31 01:29:57 +000019#define CONFIG_MPC5200
Anatolij Gustschin80869882014-10-21 22:31:26 +020020#define CONFIG_DISPLAY_BOARDINFO
Anatolij Gustschin4387cf12012-08-31 01:29:57 +000021
22#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
23
24#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
25#if defined(CONFIG_CMD_KGDB)
26/* log base 2 of the above value */
27#define CONFIG_SYS_CACHELINE_SHIFT 5
28#endif
29
30/*
31#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
32 CONFIG_SYS_POST_I2C)
33*/
34
35#ifdef CONFIG_POST
36/* preserve space for the post_word at end of on-chip SRAM */
37#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
38#endif
39
40/*
41 * Serial console configuration
42 */
43#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */
44#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
45#define CONFIG_SYS_BAUDRATE_TABLE \
46 { 9600, 19200, 38400, 57600, 115200, 230400 }
47
48/*
49 * PCI Mapping:
50 * 0x40000000 - 0x4fffffff - PCI Memory
51 * 0x50000000 - 0x50ffffff - PCI IO Space
52 */
53#undef CONFIG_PCI
54#define CONFIG_PCI_PNP 1
55
56#define CONFIG_PCI_MEM_BUS 0x40000000
57#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
58#define CONFIG_PCI_MEM_SIZE 0x10000000
59
60#define CONFIG_PCI_IO_BUS 0x50000000
61#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
62#define CONFIG_PCI_IO_SIZE 0x01000000
63
64#define CONFIG_SYS_XLB_PIPELINING 1
65
66/* Partitions */
67#define CONFIG_MAC_PARTITION
68#define CONFIG_DOS_PARTITION
69#define CONFIG_ISO_PARTITION
70
71#define CONFIG_TIMESTAMP /* Print image info with timestamp */
72
73#define CONFIG_SYS_ALT_MEMTEST /* Much more complex memory test */
74
75/*
76 * Supported commands
77 */
Anatolij Gustschin4387cf12012-08-31 01:29:57 +000078#define CONFIG_CMD_EEPROM
79#define CONFIG_CMD_FAT
80#define CONFIG_CMD_I2C
81#define CONFIG_CMD_MII
82#define CONFIG_CMD_PING
83#define CONFIG_CMD_DHCP
84#ifdef CONFIG_PCI
85#define CONFIG_CMD_PCI
86#endif
87#ifdef CONFIG_POST
88#define CONFIG_CMD_DIAG
89#endif
90
91#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
92/* Boot low with 16 or 32 MB Flash */
93#define CONFIG_SYS_LOWBOOT 1
94#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
95#error "CONFIG_SYS_TEXT_BASE value is invalid"
96#endif
97
Anatolij Gustschin4387cf12012-08-31 01:29:57 +000098#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
99
100#define CONFIG_PREBOOT "run master"
101
102#undef CONFIG_BOOTARGS
103
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000104#if !defined(CONFIG_CONSOLE_DEV)
105#define CONFIG_CONSOLE_DEV "ttyPSC1"
106#endif
107
108/*
109 * Default environment for booting old and new kernel versions
110 */
111#define CONFIG_IFM_DEFAULT_ENV_OLD \
112 "flash_self_old=run ramargs addip addmem;" \
113 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
114 "flash_nfs_old=run nfsargs addip addmem;" \
115 "bootm ${kernel_addr}\0" \
116 "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \
117 "run nfsargs addip addmem;" \
118 "bootm ${kernel_addr_r}\0"
119
120#define CONFIG_IFM_DEFAULT_ENV_NEW \
121 "fdt_addr_r=900000\0" \
122 "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0" \
123 "flash_self=run ramargs addip addtty addmisc;" \
124 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
125 "flash_nfs=run nfsargs addip addtty addmisc;" \
126 "bootm ${kernel_addr} - ${fdt_addr}\0" \
127 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
128 "tftp ${fdt_addr_r} ${fdt_file}; " \
129 "run nfsargs addip addtty addmisc;" \
130 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
131
132#define CONFIG_IFM_DEFAULT_ENV_SETTINGS \
133 "IOpin=0x64\0" \
134 "addip=setenv bootargs ${bootargs} " \
135 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
136 ":${hostname}:${netdev}:off panic=1\0" \
137 "addmem=setenv bootargs ${bootargs} ${memlimit}\0" \
138 "addmisc=sete bootargs ${bootargs} ${miscargs}\0" \
139 "addtty=sete bootargs ${bootargs} console=" \
140 CONFIG_CONSOLE_DEV ",${baudrate}\0" \
141 "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
142 "kernel_addr_r=600000\0" \
143 "initrd_high=0x03e00000\0" \
144 "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200145 "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000146 "netdev=eth0\0" \
147 "nfsargs=setenv bootargs root=/dev/nfs rw " \
148 "nfsroot=${serverip}:${rootpath}\0" \
149 "ramargs=setenv bootargs root=/dev/ram rw\0" \
150 "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
151 "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
152 "cp.b ${fileaddr} ${linbot} ${filesize}\0" \
153 "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
154 "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};" \
155 "cp.b ${fileaddr} ${rambot} ${filesize}\0" \
156 "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0" \
157 "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};" \
158 "cp.b ${fileaddr} ${jffbot} ${filesize}\0" \
159 "rootpath=/opt/eldk/ppc_6xx\0" \
160 "uboname=" CONFIG_BOARD_NAME \
161 "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0" \
162 "progubo=tftp 200000 ${uboname};" \
163 "protect off ${ubobot} ${ubotop};" \
164 "erase ${ubobot} ${ubotop};" \
165 "cp.b ${fileaddr} ${ubobot} ${filesize}\0" \
166 "unlock=yes\0" \
167 "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;" \
168 "setenv bootdelay 1;" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200169 "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" " \
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000170 BOARD_POST_CRC32_END";" \
171 "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
172
173#define CONFIG_BOOTCOMMAND "run post"
174
175/*
176 * IPB Bus clocking configuration.
177 */
178#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
179
180#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
181/*
182 * PCI Bus clocking configuration
183 *
184 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
185 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
186 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
187 */
188#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
189#endif
190
191/*
192 * I2C configuration
193 */
194#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
195#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 or #2 */
196#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
197#define CONFIG_SYS_I2C_SLAVE 0x7F
198
199/*
200 * EEPROM configuration:
201 *
202 * O2DNT board is equiped with Ramtron FRAM device FM24CL16
203 * 16 Kib Ferroelectric Nonvolatile serial RAM memory
204 * organized as 2048 x 8 bits and addressable as eight I2C devices
205 * 0x50 ... 0x57 each 256 bytes in size
206 *
207 */
208#define CONFIG_SYS_I2C_FRAM
209#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
210#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
211#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
212/*
213 * There is no write delay with FRAM, write operations are performed at bus
214 * speed. Thus, no status polling or write delay is needed.
215 */
216
217/*
218 * Flash configuration
219 */
220#define CONFIG_SYS_FLASH_CFI 1
221#define CONFIG_FLASH_CFI_DRIVER 1
222#define CONFIG_FLASH_16BIT
223#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
224#define CONFIG_SYS_FLASH_CFI_AMD_RESET
225#define CONFIG_SYS_FLASH_EMPTY_INFO
226
227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
228#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
229#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Erase Timeout (in ms) */
230#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (in ms) */
231/* Timeout for Flash Clear Lock Bits (in ms) */
232#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
233/* "Real" (hardware) sectors protection */
234#define CONFIG_SYS_FLASH_PROTECTION
235
236/*
237 * Environment settings
238 */
239#define CONFIG_ENV_IS_IN_FLASH 1
240#define CONFIG_ENV_SIZE 0x20000
241#define CONFIG_ENV_SECT_SIZE 0x20000
242#define CONFIG_ENV_OVERWRITE 1
243#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
244
245/*
246 * Memory map
247 */
248#define CONFIG_SYS_MBAR 0xF0000000
249#define CONFIG_SYS_SDRAM_BASE 0x00000000
250#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
251
252/* Use SRAM until RAM will be available */
253#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
254#ifdef CONFIG_POST
255/* preserve space for the post_word at end of on-chip SRAM */
256#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
257#else
258/* End of used area in DPRAM */
259#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
260#endif
261
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000262#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900263 GENERATED_GBL_DATA_SIZE)
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000264#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
265
266#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
267#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* 192 kB for Monitor */
268#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
269#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial map for Linux */
270
271#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
272#define CONFIG_SYS_RAMBOOT 1
273#endif
274
275/*
276 * Ethernet configuration
277 */
278#define CONFIG_MPC5xxx_FEC
279#define CONFIG_MPC5xxx_FEC_MII100
280#define CONFIG_PHY_ADDR 0x00
281#define CONFIG_RESET_PHY_R
282
283/*
284 * GPIO configuration
285 */
286#define CONFIG_SYS_GPIO_DATADIR 0x00000064 /* PSC1_2, PSC2_1,2 output */
287#define CONFIG_SYS_GPIO_OPENDRAIN 0x00000000 /* No open drain */
288#define CONFIG_SYS_GPIO_DATAVALUE 0x00000000 /* PSC1_1 to 1, rest to 0 */
289#define CONFIG_SYS_GPIO_ENABLE 0x00000064 /* PSC1_2, PSC2_1,2 enable */
290
291/*
292 * Miscellaneous configurable options
293 */
294#define CONFIG_SYS_LONGHELP /* undef to save memory */
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000295#define CONFIG_CMDLINE_EDITING
296#define CONFIG_SYS_HUSH_PARSER
297
298#if defined(CONFIG_CMD_KGDB)
299#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
300#else
301#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
302#endif
303/* Print Buffer Size */
304#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
305 sizeof(CONFIG_SYS_PROMPT) + 16)
306/* max number of command args */
307#define CONFIG_SYS_MAXARGS 16
308/* Boot Argument Buffer Size */
309#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
310
311/* default load address */
312#define CONFIG_SYS_LOAD_ADDR 0x100000
313
314/* decrementer freq: 1 ms ticks */
Anatolij Gustschin4387cf12012-08-31 01:29:57 +0000315
316/*
317 * Various low-level settings
318 */
319#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
320#define CONFIG_SYS_HID0_FINAL HID0_ICE
321
322#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
323#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
324#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
325#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
326
327#define CONFIG_BOARD_EARLY_INIT_R
328
329#define CONFIG_SYS_CS_BURST 0x00000000
330#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
331
332/*
333 * DT support
334 */
335#define CONFIG_OF_LIBFDT 1
336#define CONFIG_OF_BOARD_SETUP 1
337
338#define OF_CPU "PowerPC,5200@0"
339#define OF_SOC "soc5200@f0000000"
340#define OF_TBCLK (bd->bi_busfreq / 4)
341
342#endif /* __O2D_CONFIG_H */