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Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Timur Tabic59e1b42010-06-14 15:28:24 -05007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
Tang Yuantian840a5182014-11-07 14:46:18 +080014#define CONFIG_SYS_GENERIC_BOARD
15#define CONFIG_DISPLAY_BOARDINFO
16
Jiang Yutang9899ac12011-01-24 18:21:15 +080017#ifdef CONFIG_36BIT
18#define CONFIG_PHYS_64BIT
19#endif
20
Matthew McClintockaf253602012-05-18 06:04:17 +000021#ifdef CONFIG_SDCARD
Ying Zhang7c8eea52013-08-16 15:16:12 +080022#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
23#define CONFIG_SPL_ENV_SUPPORT
24#define CONFIG_SPL_SERIAL_SUPPORT
25#define CONFIG_SPL_MMC_SUPPORT
26#define CONFIG_SPL_MMC_MINIMAL
27#define CONFIG_SPL_FLUSH_IMAGE
28#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
29#define CONFIG_SPL_LIBGENERIC_SUPPORT
30#define CONFIG_SPL_LIBCOMMON_SUPPORT
31#define CONFIG_SPL_I2C_SUPPORT
32#define CONFIG_FSL_LAW /* Use common FSL init code */
33#define CONFIG_SYS_TEXT_BASE 0x11001000
34#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080035#define CONFIG_SPL_PAD_TO 0x20000
36#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053037#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080038#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
39#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080040#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080041#define CONFIG_SYS_MPC85XX_NO_RESETVEC
42#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
43#define CONFIG_SPL_MMC_BOOT
44#ifdef CONFIG_SPL_BUILD
45#define CONFIG_SPL_COMMON_INIT_DDR
46#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000047#endif
48
49#ifdef CONFIG_SPIFLASH
Ying Zhang382ce7e2013-08-16 15:16:14 +080050#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
51#define CONFIG_SPL_ENV_SUPPORT
52#define CONFIG_SPL_SERIAL_SUPPORT
53#define CONFIG_SPL_SPI_SUPPORT
54#define CONFIG_SPL_SPI_FLASH_SUPPORT
55#define CONFIG_SPL_SPI_FLASH_MINIMAL
56#define CONFIG_SPL_FLUSH_IMAGE
57#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
58#define CONFIG_SPL_LIBGENERIC_SUPPORT
59#define CONFIG_SPL_LIBCOMMON_SUPPORT
60#define CONFIG_SPL_I2C_SUPPORT
61#define CONFIG_FSL_LAW /* Use common FSL init code */
62#define CONFIG_SYS_TEXT_BASE 0x11001000
63#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080064#define CONFIG_SPL_PAD_TO 0x20000
65#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053066#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080067#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
68#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080069#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080070#define CONFIG_SYS_MPC85XX_NO_RESETVEC
71#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
72#define CONFIG_SPL_SPI_BOOT
73#ifdef CONFIG_SPL_BUILD
74#define CONFIG_SPL_COMMON_INIT_DDR
75#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000076#endif
77
Matthew McClintockf45210d2013-02-18 10:02:19 +000078#define CONFIG_NAND_FSL_ELBC
York Sun9407c3f2013-12-17 11:21:08 -080079#define CONFIG_SYS_NAND_MAX_ECCPOS 56
80#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockf45210d2013-02-18 10:02:19 +000081
82#ifdef CONFIG_NAND
Ying Zhang5d97fe22013-08-16 15:16:16 +080083#ifdef CONFIG_TPL_BUILD
84#define CONFIG_SPL_NAND_BOOT
85#define CONFIG_SPL_FLUSH_IMAGE
86#define CONFIG_SPL_ENV_SUPPORT
87#define CONFIG_SPL_NAND_INIT
88#define CONFIG_SPL_SERIAL_SUPPORT
89#define CONFIG_SPL_LIBGENERIC_SUPPORT
90#define CONFIG_SPL_LIBCOMMON_SUPPORT
91#define CONFIG_SPL_I2C_SUPPORT
92#define CONFIG_SPL_NAND_SUPPORT
93#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
94#define CONFIG_SPL_COMMON_INIT_DDR
95#define CONFIG_SPL_MAX_SIZE (128 << 10)
96#define CONFIG_SPL_TEXT_BASE 0xf8f81000
97#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053098#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang5d97fe22013-08-16 15:16:16 +080099#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
100#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
101#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
102#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000103#define CONFIG_SPL_INIT_MINIMAL
104#define CONFIG_SPL_SERIAL_SUPPORT
105#define CONFIG_SPL_NAND_SUPPORT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000106#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800107#define CONFIG_SPL_TEXT_BASE 0xff800000
108#define CONFIG_SPL_MAX_SIZE 4096
109#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
110#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
111#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
112#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
113#endif
114#define CONFIG_SPL_PAD_TO 0x20000
115#define CONFIG_TPL_PAD_TO 0x20000
116#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
117#define CONFIG_SYS_TEXT_BASE 0x11001000
118#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockf45210d2013-02-18 10:02:19 +0000119#endif
120
Timur Tabic59e1b42010-06-14 15:28:24 -0500121/* High Level Configuration Options */
122#define CONFIG_BOOKE /* BOOKE */
123#define CONFIG_E500 /* BOOKE e500 family */
Timur Tabic59e1b42010-06-14 15:28:24 -0500124#define CONFIG_P1022
125#define CONFIG_P1022DS
126#define CONFIG_MP /* support multiple processors */
127
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200128#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530129#define CONFIG_SYS_TEXT_BASE 0xeff40000
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200130#endif
131
Kumar Gala7a577fd2011-01-12 02:48:53 -0600132#ifndef CONFIG_RESET_VECTOR_ADDRESS
133#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
134#endif
135
Timur Tabic59e1b42010-06-14 15:28:24 -0500136#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
137#define CONFIG_PCI /* Enable PCI/PCIE */
138#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
139#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
140#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
141#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
142#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
143#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
144
Timur Tabic59e1b42010-06-14 15:28:24 -0500145#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -0500146
147#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500148#define CONFIG_ADDR_MAP
149#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800150#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500151
152#define CONFIG_FSL_LAW /* Use common FSL init code */
153
154#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
155#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
156#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
157
158/*
159 * These can be toggled for performance analysis, otherwise use default.
160 */
161#define CONFIG_L2_CACHE
162#define CONFIG_BTB
163
164#define CONFIG_SYS_MEMTEST_START 0x00000000
165#define CONFIG_SYS_MEMTEST_END 0x7fffffff
166
Timur Tabie46fedf2011-08-04 18:03:41 -0500167#define CONFIG_SYS_CCSRBAR 0xffe00000
168#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -0500169
Matthew McClintockf45210d2013-02-18 10:02:19 +0000170/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
171 SPL code*/
172#ifdef CONFIG_SPL_BUILD
173#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
174#endif
175
176
Timur Tabic59e1b42010-06-14 15:28:24 -0500177/* DDR Setup */
178#define CONFIG_DDR_SPD
179#define CONFIG_VERY_BIG_RAM
York Sun5614e712013-09-30 09:22:09 -0700180#define CONFIG_SYS_FSL_DDR3
Timur Tabic59e1b42010-06-14 15:28:24 -0500181
182#ifdef CONFIG_DDR_ECC
183#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
184#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
185#endif
186
187#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
188#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
189
190#define CONFIG_NUM_DDR_CONTROLLERS 1
191#define CONFIG_DIMM_SLOTS_PER_CTLR 1
192#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
193
194/* I2C addresses of SPD EEPROMs */
195#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -0600196#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500197
Matthew McClintockf45210d2013-02-18 10:02:19 +0000198/* These are used when DDR doesn't use SPD. */
199#define CONFIG_SYS_SDRAM_SIZE 2048
200#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
201#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
202#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
203#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
204#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
205#define CONFIG_SYS_DDR_TIMING_3 0x00010000
206#define CONFIG_SYS_DDR_TIMING_0 0x40110104
207#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
208#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
209#define CONFIG_SYS_DDR_MODE_1 0x00441221
210#define CONFIG_SYS_DDR_MODE_2 0x00000000
211#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
212#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
213#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
214#define CONFIG_SYS_DDR_CONTROL 0xc7000008
215#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
216#define CONFIG_SYS_DDR_TIMING_4 0x00220001
217#define CONFIG_SYS_DDR_TIMING_5 0x02401400
218#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
219#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
220
221
Timur Tabic59e1b42010-06-14 15:28:24 -0500222/*
223 * Memory map
224 *
225 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
226 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
227 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
228 *
229 * Localbus cacheable (TBD)
230 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
231 *
232 * Localbus non-cacheable
233 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
234 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockf45210d2013-02-18 10:02:19 +0000235 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabic59e1b42010-06-14 15:28:24 -0500236 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
237 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
238 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
239 */
240
241/*
242 * Local Bus Definitions
243 */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000244#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800245#ifdef CONFIG_PHYS_64BIT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000246#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800247#else
248#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
249#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500250
251#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockf45210d2013-02-18 10:02:19 +0000252 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabic59e1b42010-06-14 15:28:24 -0500253#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
254
Matthew McClintockf45210d2013-02-18 10:02:19 +0000255#ifdef CONFIG_NAND
256#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
257#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
258#else
Timur Tabic59e1b42010-06-14 15:28:24 -0500259#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
260#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000261#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500262
Matthew McClintockf45210d2013-02-18 10:02:19 +0000263#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabic59e1b42010-06-14 15:28:24 -0500264#define CONFIG_SYS_FLASH_QUIET_TEST
265#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
266
Matthew McClintockf45210d2013-02-18 10:02:19 +0000267#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500268#define CONFIG_SYS_MAX_FLASH_SECT 1024
269
Matthew McClintockf45210d2013-02-18 10:02:19 +0000270#ifndef CONFIG_SYS_MONITOR_BASE
271#ifdef CONFIG_SPL_BUILD
272#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
273#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200274#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000275#endif
276#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500277
278#define CONFIG_FLASH_CFI_DRIVER
279#define CONFIG_SYS_FLASH_CFI
280#define CONFIG_SYS_FLASH_EMPTY_INFO
281
Matthew McClintockf45210d2013-02-18 10:02:19 +0000282/* Nand Flash */
283#if defined(CONFIG_NAND_FSL_ELBC)
284#define CONFIG_SYS_NAND_BASE 0xff800000
285#ifdef CONFIG_PHYS_64BIT
286#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
287#else
288#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
289#endif
290
Ying Zhang5d97fe22013-08-16 15:16:16 +0800291#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockf45210d2013-02-18 10:02:19 +0000292#define CONFIG_SYS_MAX_NAND_DEVICE 1
Matthew McClintockf45210d2013-02-18 10:02:19 +0000293#define CONFIG_CMD_NAND 1
Ying Zhang5d97fe22013-08-16 15:16:16 +0800294#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000295#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
296
297/* NAND flash config */
298#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
299 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
300 | BR_PS_8 /* Port Size = 8 bit */ \
301 | BR_MS_FCM /* MSEL = FCM */ \
302 | BR_V) /* valid */
303#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
304 | OR_FCM_PGS /* Large Page*/ \
305 | OR_FCM_CSCT \
306 | OR_FCM_CST \
307 | OR_FCM_CHT \
308 | OR_FCM_SCY_1 \
309 | OR_FCM_TRLX \
310 | OR_FCM_EHTR)
311#ifdef CONFIG_NAND
312#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
313#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
314#else
315#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
316#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
317#endif
318
319#endif /* CONFIG_NAND_FSL_ELBC */
320
Timur Tabic59e1b42010-06-14 15:28:24 -0500321#define CONFIG_BOARD_EARLY_INIT_F
322#define CONFIG_BOARD_EARLY_INIT_R
323#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500324#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500325
326#define CONFIG_FSL_NGPIXIS
327#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800328#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500329#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800330#else
331#define PIXIS_BASE_PHYS PIXIS_BASE
332#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500333
334#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
335#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
336
337#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800338#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500339#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockf45210d2013-02-18 10:02:19 +0000340#define PIXIS_SPD 0x07
341#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800342#define PIXIS_ELBC_SPI_MASK 0xc0
343#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500344
345#define CONFIG_SYS_INIT_RAM_LOCK
346#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200347#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500348
Timur Tabic59e1b42010-06-14 15:28:24 -0500349#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200350 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500351#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
352
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530353#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang07b5edc2011-11-02 09:16:44 +0800354#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabic59e1b42010-06-14 15:28:24 -0500355
356/*
Ying Zhang7c8eea52013-08-16 15:16:12 +0800357 * Config the L2 Cache as L2 SRAM
358*/
359#if defined(CONFIG_SPL_BUILD)
Ying Zhang382ce7e2013-08-16 15:16:14 +0800360#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800361#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
362#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
363#define CONFIG_SYS_L2_SIZE (256 << 10)
364#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
365#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang27585bd2014-01-24 15:50:08 +0800366#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800367#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
Ying Zhang27585bd2014-01-24 15:50:08 +0800368#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
369#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800370#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800371#elif defined(CONFIG_NAND)
372#ifdef CONFIG_TPL_BUILD
373#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
374#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
375#define CONFIG_SYS_L2_SIZE (256 << 10)
376#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
377#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
378#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
379#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
380#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
381#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
382#else
383#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
384#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
385#define CONFIG_SYS_L2_SIZE (256 << 10)
386#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
387#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
388#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
389#endif
Ying Zhang7c8eea52013-08-16 15:16:12 +0800390#endif
391#endif
392
393/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500394 * Serial Port
395 */
396#define CONFIG_CONS_INDEX 1
397#define CONFIG_SYS_NS16550
398#define CONFIG_SYS_NS16550_SERIAL
399#define CONFIG_SYS_NS16550_REG_SIZE 1
400#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800401#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000402#define CONFIG_NS16550_MIN_FUNCTIONS
403#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500404
405#define CONFIG_SYS_BAUDRATE_TABLE \
406 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
407
408#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
409#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
410
411/* Use the HUSH parser */
412#define CONFIG_SYS_HUSH_PARSER
Timur Tabic59e1b42010-06-14 15:28:24 -0500413
Timur Tabic59e1b42010-06-14 15:28:24 -0500414/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500415
Timur Tabid5e01e42010-09-24 01:25:53 +0200416#ifdef CONFIG_FSL_DIU_FB
417#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
418#define CONFIG_VIDEO
419#define CONFIG_CMD_BMP
Timur Tabic59e1b42010-06-14 15:28:24 -0500420#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -0600421#define CONFIG_VIDEO_SW_CURSOR
Timur Tabic59e1b42010-06-14 15:28:24 -0500422#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabid5e01e42010-09-24 01:25:53 +0200423#define CONFIG_VIDEO_LOGO
424#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500425#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
426/*
427 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
428 * disable empty flash sector detection, which is I/O-intensive.
429 */
430#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500431#endif
432
Timur Tabiba8e76b2011-04-11 14:18:22 -0500433#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800434#endif
435
436#ifdef CONFIG_ATI
437#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
438#define CONFIG_VIDEO
439#define CONFIG_BIOSEMU
440#define CONFIG_VIDEO_SW_CURSOR
441#define CONFIG_ATI_RADEON_FB
442#define CONFIG_VIDEO_LOGO
443#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
444#define CONFIG_CFB_CONSOLE
445#define CONFIG_VGA_AS_SINGLE_DEVICE
446#endif
447
Timur Tabic59e1b42010-06-14 15:28:24 -0500448/*
449 * Pass open firmware flat tree
450 */
451#define CONFIG_OF_LIBFDT
452#define CONFIG_OF_BOARD_SETUP
453#define CONFIG_OF_STDOUT_VIA_ALIAS
454
455/* new uImage format support */
456#define CONFIG_FIT
457#define CONFIG_FIT_VERBOSE
458
459/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200460#define CONFIG_SYS_I2C
461#define CONFIG_SYS_I2C_FSL
462#define CONFIG_SYS_FSL_I2C_SPEED 400000
463#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
464#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
465#define CONFIG_SYS_FSL_I2C2_SPEED 400000
466#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
467#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabic59e1b42010-06-14 15:28:24 -0500468#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabic59e1b42010-06-14 15:28:24 -0500469
470/*
471 * I2C2 EEPROM
472 */
473#define CONFIG_ID_EEPROM
474#define CONFIG_SYS_I2C_EEPROM_NXID
475#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
476#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
477#define CONFIG_SYS_EEPROM_BUS_NUM 1
478
479/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800480 * eSPI - Enhanced SPI
481 */
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800482#define CONFIG_SPI_FLASH_SPANSION
483
484#define CONFIG_HARD_SPI
485#define CONFIG_FSL_ESPI
486
487#define CONFIG_CMD_SF
488#define CONFIG_SF_DEFAULT_SPEED 10000000
489#define CONFIG_SF_DEFAULT_MODE 0
490
491/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500492 * General PCI
493 * Memory space is mapped 1-1, but I/O space must start from 0.
494 */
495
496/* controller 1, Slot 2, tgtid 1, Base address a000 */
497#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800498#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500499#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
500#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800501#else
502#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
503#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
504#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500505#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
506#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
507#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800508#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500509#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800510#else
511#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
512#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500513#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
514
515/* controller 2, direct to uli, tgtid 2, Base address 9000 */
516#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800517#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500518#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
519#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800520#else
521#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
522#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
523#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500524#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
525#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
526#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800527#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500528#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800529#else
530#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
531#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500532#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
533
534/* controller 3, Slot 1, tgtid 3, Base address b000 */
535#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800536#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500537#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
538#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800539#else
540#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
541#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
542#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500543#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
544#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
545#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800546#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500547#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800548#else
549#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
550#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500551#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
552
553#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000554#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabic59e1b42010-06-14 15:28:24 -0500555#define CONFIG_PCI_PNP /* do pci plug-and-play */
556#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
557#endif
558
559/* SATA */
560#define CONFIG_LIBATA
561#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000562#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500563
564#define CONFIG_SYS_SATA_MAX_DEVICE 2
565#define CONFIG_SATA1
566#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
567#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
568#define CONFIG_SATA2
569#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
570#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
571
572#ifdef CONFIG_FSL_SATA
573#define CONFIG_LBA48
574#define CONFIG_CMD_SATA
575#define CONFIG_DOS_PARTITION
576#define CONFIG_CMD_EXT2
577#endif
578
579#define CONFIG_MMC
580#ifdef CONFIG_MMC
581#define CONFIG_CMD_MMC
582#define CONFIG_FSL_ESDHC
583#define CONFIG_GENERIC_MMC
584#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
585#endif
586
587#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
588#define CONFIG_CMD_EXT2
589#define CONFIG_CMD_FAT
590#define CONFIG_DOS_PARTITION
591#endif
592
593#define CONFIG_TSEC_ENET
594#ifdef CONFIG_TSEC_ENET
595
596#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500597
598#define CONFIG_MII /* MII PHY management */
599#define CONFIG_TSEC1 1
600#define CONFIG_TSEC1_NAME "eTSEC1"
601#define CONFIG_TSEC2 1
602#define CONFIG_TSEC2_NAME "eTSEC2"
603
604#define TSEC1_PHY_ADDR 1
605#define TSEC2_PHY_ADDR 2
606
607#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
608#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
609
610#define TSEC1_PHYIDX 0
611#define TSEC2_PHYIDX 0
612
613#define CONFIG_ETHPRIME "eTSEC1"
614
615#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
616#endif
617
618/*
Yangbo Lu94b383e2014-10-16 10:58:55 +0800619 * Dynamic MTD Partition support with mtdparts
620 */
621#define CONFIG_MTD_DEVICE
622#define CONFIG_MTD_PARTITIONS
623#define CONFIG_CMD_MTDPARTS
624#define CONFIG_FLASH_CFI_MTD
625#ifdef CONFIG_PHYS_64BIT
626#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
627#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
628 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
629 "512k(dtb),768k(u-boot)"
630#else
631#define MTDIDS_DEFAULT "nor0=e8000000.nor"
632#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
633 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
634 "512k(dtb),768k(u-boot)"
635#endif
636
637/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500638 * Environment
639 */
Ying Zhang382ce7e2013-08-16 15:16:14 +0800640#ifdef CONFIG_SPIFLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000641#define CONFIG_ENV_IS_IN_SPI_FLASH
642#define CONFIG_ENV_SPI_BUS 0
643#define CONFIG_ENV_SPI_CS 0
644#define CONFIG_ENV_SPI_MAX_HZ 10000000
645#define CONFIG_ENV_SPI_MODE 0
646#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
647#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
648#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhang7c8eea52013-08-16 15:16:12 +0800649#elif defined(CONFIG_SDCARD)
Matthew McClintockaf253602012-05-18 06:04:17 +0000650#define CONFIG_ENV_IS_IN_MMC
Ying Zhang7c8eea52013-08-16 15:16:12 +0800651#define CONFIG_FSL_FIXED_MMC_LOCATION
Timur Tabic59e1b42010-06-14 15:28:24 -0500652#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000653#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockf45210d2013-02-18 10:02:19 +0000654#elif defined(CONFIG_NAND)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800655#ifdef CONFIG_TPL_BUILD
656#define CONFIG_ENV_SIZE 0x2000
657#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
658#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000659#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800660#endif
661#define CONFIG_ENV_IS_IN_NAND
662#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockaf253602012-05-18 06:04:17 +0000663#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000664#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockaf253602012-05-18 06:04:17 +0000665#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
666#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
667#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000668#else
669#define CONFIG_ENV_IS_IN_FLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000670#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Matthew McClintockaf253602012-05-18 06:04:17 +0000671#define CONFIG_ENV_SIZE 0x2000
672#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
673#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500674
675#define CONFIG_LOADS_ECHO
676#define CONFIG_SYS_LOADS_BAUD_CHANGE
677
678/*
679 * Command line configuration.
680 */
Kumar Gala79ee3442010-06-09 22:59:41 -0500681#define CONFIG_CMD_ELF
682#define CONFIG_CMD_ERRATA
Timur Tabic59e1b42010-06-14 15:28:24 -0500683#define CONFIG_CMD_IRQ
Timur Tabic59e1b42010-06-14 15:28:24 -0500684#define CONFIG_CMD_I2C
685#define CONFIG_CMD_MII
Kumar Gala79ee3442010-06-09 22:59:41 -0500686#define CONFIG_CMD_PING
Matthew McClintockb8339e22010-12-17 17:26:41 -0600687#define CONFIG_CMD_REGINFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500688
689#ifdef CONFIG_PCI
690#define CONFIG_CMD_PCI
Timur Tabic59e1b42010-06-14 15:28:24 -0500691#endif
692
693/*
694 * USB
695 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000696#define CONFIG_HAS_FSL_DR_USB
697#ifdef CONFIG_HAS_FSL_DR_USB
Timur Tabic59e1b42010-06-14 15:28:24 -0500698#define CONFIG_USB_EHCI
699
700#ifdef CONFIG_USB_EHCI
701#define CONFIG_CMD_USB
702#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
703#define CONFIG_USB_EHCI_FSL
704#define CONFIG_USB_STORAGE
705#define CONFIG_CMD_FAT
706#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000707#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500708
709/*
710 * Miscellaneous configurable options
711 */
712#define CONFIG_SYS_LONGHELP /* undef to save memory */
713#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500714#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabic59e1b42010-06-14 15:28:24 -0500715#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabic59e1b42010-06-14 15:28:24 -0500716#ifdef CONFIG_CMD_KGDB
717#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
718#else
719#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
720#endif
721/* Print Buffer Size */
722#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
723#define CONFIG_SYS_MAXARGS 16
724#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Timur Tabic59e1b42010-06-14 15:28:24 -0500725
726/*
727 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500728 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500729 * the maximum mapped by the Linux kernel during initialization.
730 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500731#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
732#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500733
Timur Tabic59e1b42010-06-14 15:28:24 -0500734#ifdef CONFIG_CMD_KGDB
735#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabic59e1b42010-06-14 15:28:24 -0500736#endif
737
738/*
739 * Environment Configuration
740 */
741
742#define CONFIG_HOSTNAME p1022ds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000743#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000744#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500745#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
746
747#define CONFIG_LOADADDR 1000000
748
749#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Timur Tabic59e1b42010-06-14 15:28:24 -0500750
751#define CONFIG_BAUDRATE 115200
752
Timur Tabi84e34b62012-05-04 12:21:29 +0000753#define CONFIG_EXTRA_ENV_SETTINGS \
754 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200755 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
756 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000757 "tftpflash=tftpboot $loadaddr $uboot && " \
758 "protect off $ubootaddr +$filesize && " \
759 "erase $ubootaddr +$filesize && " \
760 "cp.b $loadaddr $ubootaddr $filesize && " \
761 "protect on $ubootaddr +$filesize && " \
762 "cmp.b $loadaddr $ubootaddr $filesize\0" \
763 "consoledev=ttyS0\0" \
764 "ramdiskaddr=2000000\0" \
765 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
766 "fdtaddr=c00000\0" \
767 "fdtfile=p1022ds.dtb\0" \
768 "bdev=sda3\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500769 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500770
771#define CONFIG_HDBOOT \
772 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000773 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500774 "tftp $loadaddr $bootfile;" \
775 "tftp $fdtaddr $fdtfile;" \
776 "bootm $loadaddr - $fdtaddr"
777
778#define CONFIG_NFSBOOTCOMMAND \
779 "setenv bootargs root=/dev/nfs rw " \
780 "nfsroot=$serverip:$rootpath " \
781 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000782 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500783 "tftp $loadaddr $bootfile;" \
784 "tftp $fdtaddr $fdtfile;" \
785 "bootm $loadaddr - $fdtaddr"
786
787#define CONFIG_RAMBOOTCOMMAND \
788 "setenv bootargs root=/dev/ram rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000789 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500790 "tftp $ramdiskaddr $ramdiskfile;" \
791 "tftp $loadaddr $bootfile;" \
792 "tftp $fdtaddr $fdtfile;" \
793 "bootm $loadaddr $ramdiskaddr $fdtaddr"
794
795#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
796
797#endif