| Bryan Brattlof | ee31be4 | 2022-10-24 16:53:28 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* |
| 3 | * Cadence DDR Driver |
| 4 | * |
| 5 | * Copyright (C) 2012-2022 Cadence Design Systems, Inc. |
| 6 | * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ |
| 7 | */ |
| 8 | |
| 9 | #ifndef LPDDR4_J721E_H |
| 10 | #define LPDDR4_J721E_H |
| 11 | |
| 12 | #include "lpddr4_j721e_ctl_regs_rw_masks.h" |
| 13 | |
| 14 | #define DSLICE_NUM (4U) |
| 15 | #define ASLICE_NUM (1U) |
| 16 | |
| 17 | #define DSLICE0_REG_COUNT (140U) |
| 18 | #define DSLICE1_REG_COUNT (140U) |
| 19 | #define DSLICE2_REG_COUNT (140U) |
| 20 | #define DSLICE3_REG_COUNT (140U) |
| 21 | #define ASLICE0_REG_COUNT (52U) |
| 22 | #define PHY_CORE_REG_COUNT (140U) |
| 23 | |
| 24 | #endif /* LPDDR4_J721E_H */ |