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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00002/*
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00004 */
5
Paul Burton7a9d1092013-11-09 10:22:08 +00006#ifndef _MALTA_CONFIG_H
7#define _MALTA_CONFIG_H
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00008
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00009/*
10 * System configuration
11 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000012
13/*
14 * CPU Configuration
15 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000016
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000017/*
18 * Memory map
19 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000020
Paul Burton0f832b92016-05-26 14:49:36 +010021#ifdef CONFIG_64BIT
Tom Riniaa6e94d2022-11-16 13:10:37 -050022# define CFG_SYS_SDRAM_BASE 0xffffffff80000000
Paul Burton0f832b92016-05-26 14:49:36 +010023#else
Tom Riniaa6e94d2022-11-16 13:10:37 -050024# define CFG_SYS_SDRAM_BASE 0x80000000
Paul Burton0f832b92016-05-26 14:49:36 +010025#endif
Tom Riniaa6e94d2022-11-16 13:10:37 -050026#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 MiB */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000027
Tom Rini65cc0e22022-11-16 13:10:41 -050028#define CFG_SYS_INIT_SP_OFFSET 0x400000
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000029
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000030/*
31 * Serial driver
32 */
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000033
34/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000035 * Flash configuration
36 */
Paul Burton0f832b92016-05-26 14:49:36 +010037#ifdef CONFIG_64BIT
Tom Rini65cc0e22022-11-16 13:10:41 -050038# define CFG_SYS_FLASH_BASE 0xffffffffbe000000
Paul Burton0f832b92016-05-26 14:49:36 +010039#else
Tom Rini65cc0e22022-11-16 13:10:41 -050040# define CFG_SYS_FLASH_BASE 0xbe000000
Paul Burton0f832b92016-05-26 14:49:36 +010041#endif
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000042
43/*
Paul Burtonfba6f452013-11-08 11:18:56 +000044 * Environment
45 */
Paul Burtonfba6f452013-11-08 11:18:56 +000046
47/*
Paul Burtonba21a452015-01-29 10:38:20 +000048 * IDE/ATA
49 */
Paul Burtonba21a452015-01-29 10:38:20 +000050
51/*
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000052 * Commands
53 */
Gabor Juhosfeaa6062013-05-22 03:57:42 +000054
Paul Burton7a9d1092013-11-09 10:22:08 +000055#endif /* _MALTA_CONFIG_H */