blob: 5b6f27186bf700312388cedf305abac340f2fa35 [file] [log] [blame]
wdenk8b0bfc62005-04-03 23:11:38 +00001/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * U-Boot configuration for Analogue&Micro Rattler boards.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_MPC8248
30#define CPU_ID_STR "MPC8248"
31#else
32#define CONFIG_MPC8260
33#define CPU_ID_STR "MPC8250"
34#endif /* CONFIG_MPC8248 */
35
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* Has a CPM2 */
37
wdenk8b0bfc62005-04-03 23:11:38 +000038#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
39
wdenk8b0bfc62005-04-03 23:11:38 +000040/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
41#define CONFIG_ENV_OVERWRITE
42
43/*
44 * Select serial console configuration
45 *
46 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
47 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 * for SCC).
49 */
50#define CONFIG_CONS_ON_SMC /* Console is on SMC */
51#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
52#undef CONFIG_CONS_NONE /* It's not on external UART */
53#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
54
55/*
56 * Select ethernet configuration
57 *
58 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
59 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * SCC, 1-3 for FCC)
61 *
62 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
Jon Loeliger639221c2007-07-09 17:15:49 -050063 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
64 * must be unset.
wdenk8b0bfc62005-04-03 23:11:38 +000065 */
66#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
67#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
68#undef CONFIG_ETHER_NONE /* No external Ethernet */
69
70#ifdef CONFIG_ETHER_ON_FCC
71
72#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
73
74#if (CONFIG_ETHER_INDEX == 1)
75
76/* - Rx clock is CLK11
77 * - Tx clock is CLK10
78 * - BDs/buffers on 60x bus
79 * - Full duplex
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
82#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
83#define CONFIG_SYS_CPMFCR_RAMTYPE 0
84#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenk8b0bfc62005-04-03 23:11:38 +000085
86#elif (CONFIG_ETHER_INDEX == 2)
87
88/* - Rx clock is CLK15
89 * - Tx clock is CLK14
90 * - BDs/buffers on 60x bus
91 * - Full duplex
92 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
94#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
95#define CONFIG_SYS_CPMFCR_RAMTYPE 0
96#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenk8b0bfc62005-04-03 23:11:38 +000097
98#endif /* CONFIG_ETHER_INDEX */
99
100#define CONFIG_MII /* MII PHY management */
101#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
102/*
103 * GPIO pins used for bit-banged MII communications
104 */
105#define MDIO_PORT 2 /* Port C */
106#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
107#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
108#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
109
110#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
111 else iop->pdat &= ~0x00400000
112
113#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
114 else iop->pdat &= ~0x00800000
115
116#define MIIDELAY udelay(1)
117
118#endif /* CONFIG_ETHER_ON_FCC */
119
120#ifndef CONFIG_8260_CLKIN
121#define CONFIG_8260_CLKIN 100000000 /* in Hz */
122#endif
123
124#define CONFIG_BAUDRATE 38400
125
wdenk8b0bfc62005-04-03 23:11:38 +0000126
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500127/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500128 * BOOTP options
129 */
130#define CONFIG_BOOTP_BOOTFILESIZE
131#define CONFIG_BOOTP_BOOTPATH
132#define CONFIG_BOOTP_GATEWAY
133#define CONFIG_BOOTP_HOSTNAME
134
135
136/*
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500137 * Command line configuration.
138 */
139#include <config_cmd_default.h>
140
141#define CONFIG_CMD_DHCP
142#define CONFIG_CMD_IMMAP
143#define CONFIG_CMD_JFFS2
144#define CONFIG_CMD_MII
145#define CONFIG_CMD_PING
146
wdenk8b0bfc62005-04-03 23:11:38 +0000147
148#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
149#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
150#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
151
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500152#if defined(CONFIG_CMD_KGDB)
wdenk8b0bfc62005-04-03 23:11:38 +0000153#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
154#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
155#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
156#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
157#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
158#endif
159
160#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
161#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
162
163/*
164 * Miscellaneous configurable options
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_HUSH_PARSER
167#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
168#define CONFIG_SYS_LONGHELP /* undef to save memory */
169#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500170#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk8b0bfc62005-04-03 23:11:38 +0000172#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk8b0bfc62005-04-03 23:11:38 +0000174#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
176#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk8b0bfc62005-04-03 23:11:38 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
180#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk8b0bfc62005-04-03 23:11:38 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk8b0bfc62005-04-03 23:11:38 +0000183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk8b0bfc62005-04-03 23:11:38 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk8b0bfc62005-04-03 23:11:38 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_BASE 0xFE000000
189#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200190#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
192#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenk8b0bfc62005-04-03 23:11:38 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_DIRECT_FLASH_TFTP
wdenk8b0bfc62005-04-03 23:11:38 +0000195
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500196#if defined(CONFIG_CMD_JFFS2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
198#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200199
200/*
201 * JFFS2 partitions
202 *
203 */
204/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100205#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200206#define CONFIG_JFFS2_DEV "nor0"
207#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
208#define CONFIG_JFFS2_PART_OFFSET 0x00100000
209
210/* mtdparts command line support */
211/* Note: fake mtd_id used, no linux mtd map file */
212/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100213#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200214#define MTDIDS_DEFAULT "nor0=rattler-0"
215#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
216*/
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500217#endif /* CONFIG_CMD_JFFS2 */
wdenk8b0bfc62005-04-03 23:11:38 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
220#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
221#define CONFIG_SYS_RAMBOOT
wdenk8b0bfc62005-04-03 23:11:38 +0000222#endif
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk8b0bfc62005-04-03 23:11:38 +0000225
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200226#define CONFIG_ENV_IS_IN_FLASH
wdenk8b0bfc62005-04-03 23:11:38 +0000227
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200228#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200229#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200231#endif /* CONFIG_ENV_IS_IN_FLASH */
wdenk8b0bfc62005-04-03 23:11:38 +0000232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
wdenk8b0bfc62005-04-03 23:11:38 +0000234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_IMMR 0xF0000000
wdenk8b0bfc62005-04-03 23:11:38 +0000236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
238#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
239#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
240#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
241#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk8b0bfc62005-04-03 23:11:38 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_SDRAM_BASE 0x00000000
244#define CONFIG_SYS_SDRAM_SIZE 32
245#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
246#define CONFIG_SYS_SDRAM_OR 0xFE002EC0
wdenk8b0bfc62005-04-03 23:11:38 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_BCSR 0xFC000000
wdenk8b0bfc62005-04-03 23:11:38 +0000249
250/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
wdenk8b0bfc62005-04-03 23:11:38 +0000252/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_HRCW_SLAVE1 0
254#define CONFIG_SYS_HRCW_SLAVE2 0
255#define CONFIG_SYS_HRCW_SLAVE3 0
256#define CONFIG_SYS_HRCW_SLAVE4 0
257#define CONFIG_SYS_HRCW_SLAVE5 0
258#define CONFIG_SYS_HRCW_SLAVE6 0
259#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk8b0bfc62005-04-03 23:11:38 +0000260
261#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
262#define BOOTFLAG_WARM 0x02 /* Software reboot */
263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
265#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk8b0bfc62005-04-03 23:11:38 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Jon Loeligere9a0f8f2007-07-08 15:12:40 -0500268#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk8b0bfc62005-04-03 23:11:38 +0000270#endif
271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_HID0_INIT 0
273#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
wdenk8b0bfc62005-04-03 23:11:38 +0000274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_HID2 0
wdenk8b0bfc62005-04-03 23:11:38 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_SIUMCR 0x0E04C000
278#define CONFIG_SYS_SYPCR 0xFFFFFFC3
279#define CONFIG_SYS_BCR 0x00000000
280#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk8b0bfc62005-04-03 23:11:38 +0000281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_RMR RMR_CSRE
283#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
284#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
285#define CONFIG_SYS_RCCR 0
wdenk8b0bfc62005-04-03 23:11:38 +0000286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PSDMR 0x8249A452
288#define CONFIG_SYS_PSRT 0x1F
289#define CONFIG_SYS_MPTPR 0x2000
wdenk8b0bfc62005-04-03 23:11:38 +0000290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
292#define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
293#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
294#define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
wdenk8b0bfc62005-04-03 23:11:38 +0000295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
wdenk8b0bfc62005-04-03 23:11:38 +0000297
298#endif /* __CONFIG_H */