Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 2 | /* |
| 3 | * board/renesas/eagle/eagle.c |
| 4 | * This file is Eagle board support. |
| 5 | * |
| 6 | * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | 9a3b4ce | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 10 | #include <cpu_func.h> |
Simon Glass | db41d65 | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 11 | #include <hang.h> |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 12 | #include <malloc.h> |
| 13 | #include <netdev.h> |
| 14 | #include <dm.h> |
| 15 | #include <dm/platform_data/serial_sh.h> |
| 16 | #include <asm/processor.h> |
| 17 | #include <asm/mach-types.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <linux/errno.h> |
| 20 | #include <asm/arch/sys_proto.h> |
| 21 | #include <asm/gpio.h> |
| 22 | #include <asm/arch/gpio.h> |
| 23 | #include <asm/arch/rmobile.h> |
| 24 | #include <asm/arch/rcar-mstp.h> |
| 25 | #include <asm/arch/sh_sdhi.h> |
| 26 | #include <i2c.h> |
| 27 | #include <mmc.h> |
| 28 | |
| 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
Marek Vasut | c267952 | 2018-06-16 01:16:50 +0200 | [diff] [blame] | 31 | #define CPGWPR 0xE6150900 |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 32 | #define CPGWPCR 0xE6150904 |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 33 | |
| 34 | /* PLL */ |
| 35 | #define PLL0CR 0xE61500D8 |
| 36 | #define PLL0_STC_MASK 0x7F000000 |
| 37 | #define PLL0_STC_OFFSET 24 |
| 38 | |
| 39 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
| 40 | void s_init(void) |
| 41 | { |
| 42 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
| 43 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
| 44 | u32 stc; |
| 45 | |
| 46 | /* Watchdog init */ |
| 47 | writel(0xA5A5A500, &rwdt->rwtcsra); |
| 48 | writel(0xA5A5A500, &swdt->swtcsra); |
| 49 | |
| 50 | /* CPU frequency setting. Set to 0.8GHz */ |
| 51 | stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET; |
| 52 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); |
| 53 | } |
| 54 | |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 55 | int board_early_init_f(void) |
| 56 | { |
Marek Vasut | c267952 | 2018-06-16 01:16:50 +0200 | [diff] [blame] | 57 | /* Unlock CPG access */ |
| 58 | writel(0xA5A5FFFF, CPGWPR); |
| 59 | writel(0x5A5A0000, CPGWPCR); |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 60 | |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 61 | return 0; |
| 62 | } |
| 63 | |
| 64 | int board_init(void) |
| 65 | { |
| 66 | /* adress of boot parameters */ |
| 67 | gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
| 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
Marek Vasut | d21f08b | 2017-10-09 21:08:10 +0200 | [diff] [blame] | 72 | #define RST_BASE 0xE6160000 |
| 73 | #define RST_CA57RESCNT (RST_BASE + 0x40) |
| 74 | #define RST_CA53RESCNT (RST_BASE + 0x44) |
| 75 | #define RST_RSTOUTCR (RST_BASE + 0x58) |
| 76 | #define RST_CA57_CODE 0xA5A5000F |
| 77 | #define RST_CA53_CODE 0x5A5A000F |
| 78 | |
| 79 | void reset_cpu(ulong addr) |
| 80 | { |
| 81 | unsigned long midr, cputype; |
| 82 | |
| 83 | asm volatile("mrs %0, midr_el1" : "=r" (midr)); |
| 84 | cputype = (midr >> 4) & 0xfff; |
| 85 | |
| 86 | if (cputype == 0xd03) |
| 87 | writel(RST_CA53_CODE, RST_CA53RESCNT); |
| 88 | else if (cputype == 0xd07) |
| 89 | writel(RST_CA57_CODE, RST_CA57RESCNT); |
| 90 | else |
| 91 | hang(); |
| 92 | } |