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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutd21f08b2017-10-09 21:08:10 +02002/*
3 * board/renesas/eagle/eagle.c
4 * This file is Eagle board support.
5 *
6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasutd21f08b2017-10-09 21:08:10 +02007 */
8
9#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -070010#include <cpu_func.h>
Marek Vasutd21f08b2017-10-09 21:08:10 +020011#include <malloc.h>
12#include <netdev.h>
13#include <dm.h>
14#include <dm/platform_data/serial_sh.h>
15#include <asm/processor.h>
16#include <asm/mach-types.h>
17#include <asm/io.h>
18#include <linux/errno.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/gpio.h>
21#include <asm/arch/gpio.h>
22#include <asm/arch/rmobile.h>
23#include <asm/arch/rcar-mstp.h>
24#include <asm/arch/sh_sdhi.h>
25#include <i2c.h>
26#include <mmc.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
Marek Vasutc2679522018-06-16 01:16:50 +020030#define CPGWPR 0xE6150900
Marek Vasutd21f08b2017-10-09 21:08:10 +020031#define CPGWPCR 0xE6150904
Marek Vasutd21f08b2017-10-09 21:08:10 +020032
33/* PLL */
34#define PLL0CR 0xE61500D8
35#define PLL0_STC_MASK 0x7F000000
36#define PLL0_STC_OFFSET 24
37
38#define CLK2MHZ(clk) (clk / 1000 / 1000)
39void s_init(void)
40{
41 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
42 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
43 u32 stc;
44
45 /* Watchdog init */
46 writel(0xA5A5A500, &rwdt->rwtcsra);
47 writel(0xA5A5A500, &swdt->swtcsra);
48
49 /* CPU frequency setting. Set to 0.8GHz */
50 stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
51 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
52}
53
Marek Vasutd21f08b2017-10-09 21:08:10 +020054int board_early_init_f(void)
55{
Marek Vasutc2679522018-06-16 01:16:50 +020056 /* Unlock CPG access */
57 writel(0xA5A5FFFF, CPGWPR);
58 writel(0x5A5A0000, CPGWPCR);
Marek Vasutd21f08b2017-10-09 21:08:10 +020059
Marek Vasutd21f08b2017-10-09 21:08:10 +020060 return 0;
61}
62
63int board_init(void)
64{
65 /* adress of boot parameters */
66 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
67
68 return 0;
69}
70
Marek Vasutd21f08b2017-10-09 21:08:10 +020071#define RST_BASE 0xE6160000
72#define RST_CA57RESCNT (RST_BASE + 0x40)
73#define RST_CA53RESCNT (RST_BASE + 0x44)
74#define RST_RSTOUTCR (RST_BASE + 0x58)
75#define RST_CA57_CODE 0xA5A5000F
76#define RST_CA53_CODE 0x5A5A000F
77
78void reset_cpu(ulong addr)
79{
80 unsigned long midr, cputype;
81
82 asm volatile("mrs %0, midr_el1" : "=r" (midr));
83 cputype = (midr >> 4) & 0xfff;
84
85 if (cputype == 0xd03)
86 writel(RST_CA53_CODE, RST_CA53RESCNT);
87 else if (cputype == 0xd07)
88 writel(RST_CA57_CODE, RST_CA57RESCNT);
89 else
90 hang();
91}