Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2 | /* |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 3 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. |
| 8 | * Based on code from spd_sdram.c |
| 9 | * Author: James Yang [at freescale.com] |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 13 | #include <dm.h> |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 14 | #include <i2c.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 15 | #include <fsl_ddr_sdram.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 16 | #include <fsl_ddr.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame^] | 17 | #include <init.h> |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 18 | |
York Sun | 6b9e309 | 2014-02-10 13:59:43 -0800 | [diff] [blame] | 19 | /* |
| 20 | * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view |
| 21 | * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for |
| 22 | * all Power SoCs. But it could be different for ARM SoCs. For example, |
| 23 | * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of |
| 24 | * 0x00_8000_0000 ~ 0x00_ffff_ffff |
| 25 | * 0x80_8000_0000 ~ 0xff_ffff_ffff |
| 26 | */ |
| 27 | #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY |
Mario Six | 133ec60 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 28 | #ifdef CONFIG_MPC83xx |
| 29 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE |
| 30 | #else |
York Sun | 6b9e309 | 2014-02-10 13:59:43 -0800 | [diff] [blame] | 31 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE |
| 32 | #endif |
Mario Six | 133ec60 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 33 | #endif |
York Sun | 6b9e309 | 2014-02-10 13:59:43 -0800 | [diff] [blame] | 34 | |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 35 | #ifdef CONFIG_PPC |
| 36 | #include <asm/fsl_law.h> |
| 37 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 38 | void fsl_ddr_set_lawbar( |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 39 | const common_timing_params_t *memctl_common_params, |
| 40 | unsigned int memctl_interleaved, |
| 41 | unsigned int ctrl_num); |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 42 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 43 | |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 44 | void fsl_ddr_set_intl3r(const unsigned int granule_size); |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 45 | #if defined(SPD_EEPROM_ADDRESS) || \ |
| 46 | defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ |
| 47 | defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 48 | #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) |
| 49 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 50 | [0][0] = SPD_EEPROM_ADDRESS, |
| 51 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 52 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) |
| 53 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
York Sun | 639f330 | 2011-08-26 11:32:41 -0700 | [diff] [blame] | 54 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 55 | [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ |
| 56 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 57 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) |
| 58 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 59 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 60 | [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ |
| 61 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 62 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) |
| 63 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 64 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 65 | [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ |
| 66 | [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ |
| 67 | [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ |
| 68 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 69 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) |
| 70 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 71 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 72 | [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ |
| 73 | [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ |
| 74 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 75 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) |
| 76 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 77 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 78 | [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ |
| 79 | [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ |
| 80 | [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ |
| 81 | [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ |
| 82 | [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ |
| 83 | }; |
| 84 | |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 85 | #endif |
| 86 | |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 87 | #if defined(CONFIG_DM_I2C) |
| 88 | #define DEV_TYPE struct udevice |
| 89 | #else |
| 90 | /* Local udevice */ |
| 91 | struct ludevice { |
| 92 | u8 chip; |
| 93 | }; |
| 94 | |
| 95 | #define DEV_TYPE struct ludevice |
| 96 | |
| 97 | #endif |
| 98 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 99 | #define SPD_SPA0_ADDRESS 0x36 |
| 100 | #define SPD_SPA1_ADDRESS 0x37 |
| 101 | |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 102 | static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr, |
| 103 | int alen, uint8_t *buf, int len) |
| 104 | { |
| 105 | int ret; |
| 106 | |
| 107 | #ifdef CONFIG_DM_I2C |
| 108 | ret = dm_i2c_read(dev, 0, buf, len); |
| 109 | #else |
| 110 | ret = i2c_read(dev->chip, addr, alen, buf, len); |
| 111 | #endif |
| 112 | |
| 113 | return ret; |
| 114 | } |
| 115 | |
| 116 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 117 | static int ddr_i2c_dummy_write(unsigned int chip_addr) |
| 118 | { |
| 119 | uint8_t buf = 0; |
| 120 | |
| 121 | #ifdef CONFIG_DM_I2C |
| 122 | struct udevice *dev; |
| 123 | int ret; |
| 124 | |
| 125 | ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr, |
| 126 | 1, &dev); |
| 127 | if (ret) { |
| 128 | printf("%s: Cannot find udev for a bus %d\n", __func__, |
| 129 | CONFIG_SYS_SPD_BUS_NUM); |
| 130 | return ret; |
| 131 | } |
| 132 | |
| 133 | return dm_i2c_write(dev, 0, &buf, 1); |
| 134 | #else |
| 135 | return i2c_write(chip_addr, 0, 1, &buf, 1); |
| 136 | #endif |
| 137 | |
| 138 | return 0; |
| 139 | } |
| 140 | #endif |
| 141 | |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 142 | static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) |
| 143 | { |
Valentin Longchamp | 0778bbe | 2013-10-18 11:47:19 +0200 | [diff] [blame] | 144 | int ret; |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 145 | DEV_TYPE *dev; |
Valentin Longchamp | 0778bbe | 2013-10-18 11:47:19 +0200 | [diff] [blame] | 146 | |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 147 | #if defined(CONFIG_DM_I2C) |
| 148 | ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address, |
| 149 | 1, &dev); |
| 150 | if (ret) { |
| 151 | printf("%s: Cannot find udev for a bus %d\n", __func__, |
| 152 | CONFIG_SYS_SPD_BUS_NUM); |
| 153 | return; |
| 154 | } |
| 155 | #else /* Non DM I2C support - will be removed */ |
| 156 | struct ludevice ldev = { |
| 157 | .chip = i2c_address, |
| 158 | }; |
| 159 | dev = &ldev; |
| 160 | |
Valentin Longchamp | 0778bbe | 2013-10-18 11:47:19 +0200 | [diff] [blame] | 161 | i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); |
Chuanhua Han | 0eba65d | 2019-07-10 21:00:20 +0800 | [diff] [blame] | 162 | #endif |
| 163 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 164 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 165 | /* |
| 166 | * DDR4 SPD has 384 to 512 bytes |
| 167 | * To access the lower 256 bytes, we need to set EE page address to 0 |
| 168 | * To access the upper 256 bytes, we need to set EE page address to 1 |
| 169 | * See Jedec standar No. 21-C for detail |
| 170 | */ |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 171 | ddr_i2c_dummy_write(SPD_SPA0_ADDRESS); |
| 172 | ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 173 | if (!ret) { |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 174 | ddr_i2c_dummy_write(SPD_SPA1_ADDRESS); |
| 175 | ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256), |
| 176 | min(256, |
| 177 | (int)sizeof(generic_spd_eeprom_t) |
| 178 | - 256)); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 179 | } |
Chuanhua Han | 0eba65d | 2019-07-10 21:00:20 +0800 | [diff] [blame] | 180 | |
| 181 | #else |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 182 | ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, |
| 183 | sizeof(generic_spd_eeprom_t)); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 184 | #endif |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 185 | |
| 186 | if (ret) { |
York Sun | 82968a7 | 2012-10-08 07:44:28 +0000 | [diff] [blame] | 187 | if (i2c_address == |
| 188 | #ifdef SPD_EEPROM_ADDRESS |
| 189 | SPD_EEPROM_ADDRESS |
| 190 | #elif defined(SPD_EEPROM_ADDRESS1) |
| 191 | SPD_EEPROM_ADDRESS1 |
| 192 | #endif |
| 193 | ) { |
| 194 | printf("DDR: failed to read SPD from address %u\n", |
| 195 | i2c_address); |
| 196 | } else { |
| 197 | debug("DDR: failed to read SPD from address %u\n", |
| 198 | i2c_address); |
| 199 | } |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 200 | memset(spd, 0, sizeof(generic_spd_eeprom_t)); |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | __attribute__((weak, alias("__get_spd"))) |
| 205 | void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); |
| 206 | |
York Sun | b92557c | 2015-05-28 14:54:08 +0530 | [diff] [blame] | 207 | /* This function allows boards to update SPD address */ |
| 208 | __weak void update_spd_address(unsigned int ctrl_num, |
| 209 | unsigned int slot, |
| 210 | unsigned int *addr) |
| 211 | { |
| 212 | } |
| 213 | |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 214 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 215 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 216 | { |
| 217 | unsigned int i; |
| 218 | unsigned int i2c_address = 0; |
| 219 | |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 220 | if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 221 | printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); |
| 222 | return; |
| 223 | } |
| 224 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 225 | for (i = 0; i < dimm_slots_per_ctrl; i++) { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 226 | i2c_address = spd_i2c_addr[ctrl_num][i]; |
York Sun | b92557c | 2015-05-28 14:54:08 +0530 | [diff] [blame] | 227 | update_spd_address(ctrl_num, i, &i2c_address); |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 228 | get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
| 229 | } |
| 230 | } |
| 231 | #else |
| 232 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 233 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 234 | { |
| 235 | } |
| 236 | #endif /* SPD_EEPROM_ADDRESSx */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 237 | |
| 238 | /* |
| 239 | * ASSUMPTIONS: |
| 240 | * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller |
| 241 | * - Same memory data bus width on all controllers |
| 242 | * |
| 243 | * NOTES: |
| 244 | * |
| 245 | * The memory controller and associated documentation use confusing |
| 246 | * terminology when referring to the orgranization of DRAM. |
| 247 | * |
| 248 | * Here is a terminology translation table: |
| 249 | * |
| 250 | * memory controller/documention |industry |this code |signals |
| 251 | * -------------------------------|-----------|-----------|----------------- |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 252 | * physical bank/bank |rank |rank |chip select (CS) |
| 253 | * logical bank/sub-bank |bank |bank |bank address (BA) |
| 254 | * page/row |row |page |row address |
| 255 | * ??? |column |column |column address |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 256 | * |
| 257 | * The naming confusion is further exacerbated by the descriptions of the |
| 258 | * memory controller interleaving feature, where accesses are interleaved |
| 259 | * _BETWEEN_ two seperate memory controllers. This is configured only in |
| 260 | * CS0_CONFIG[INTLV_CTL] of each memory controller. |
| 261 | * |
| 262 | * memory controller documentation | number of chip selects |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 263 | * | per memory controller supported |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 264 | * --------------------------------|----------------------------------------- |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 265 | * cache line interleaving | 1 (CS0 only) |
| 266 | * page interleaving | 1 (CS0 only) |
| 267 | * bank interleaving | 1 (CS0 only) |
| 268 | * superbank interleraving | depends on bank (chip select) |
| 269 | * | interleraving [rank interleaving] |
| 270 | * | mode used on every memory controller |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 271 | * |
| 272 | * Even further confusing is the existence of the interleaving feature |
| 273 | * _WITHIN_ each memory controller. The feature is referred to in |
| 274 | * documentation as chip select interleaving or bank interleaving, |
| 275 | * although it is configured in the DDR_SDRAM_CFG field. |
| 276 | * |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 277 | * Name of field | documentation name | this code |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 278 | * -----------------------------|-----------------------|------------------ |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 279 | * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving |
| 280 | * | interleaving |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 281 | */ |
| 282 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 283 | const char *step_string_tbl[] = { |
| 284 | "STEP_GET_SPD", |
| 285 | "STEP_COMPUTE_DIMM_PARMS", |
| 286 | "STEP_COMPUTE_COMMON_PARMS", |
| 287 | "STEP_GATHER_OPTS", |
| 288 | "STEP_ASSIGN_ADDRESSES", |
| 289 | "STEP_COMPUTE_REGS", |
| 290 | "STEP_PROGRAM_REGS", |
| 291 | "STEP_ALL" |
| 292 | }; |
| 293 | |
| 294 | const char * step_to_string(unsigned int step) { |
| 295 | |
| 296 | unsigned int s = __ilog2(step); |
| 297 | |
| 298 | if ((1 << s) != step) |
| 299 | return step_string_tbl[7]; |
| 300 | |
York Sun | 349689b | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 301 | if (s >= ARRAY_SIZE(step_string_tbl)) { |
| 302 | printf("Error for the step in %s\n", __func__); |
| 303 | s = 0; |
| 304 | } |
| 305 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 306 | return step_string_tbl[s]; |
| 307 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 308 | |
York Sun | ef00227 | 2013-03-25 07:39:35 +0000 | [diff] [blame] | 309 | static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 310 | unsigned int dbw_cap_adj[]) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 311 | { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 312 | unsigned int i, j; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 313 | unsigned long long total_mem, current_mem_base, total_ctlr_mem; |
| 314 | unsigned long long rank_density, ctlr_density = 0; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 315 | unsigned int first_ctrl = pinfo->first_ctrl; |
| 316 | unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 317 | |
| 318 | /* |
| 319 | * If a reduced data width is requested, but the SPD |
| 320 | * specifies a physically wider device, adjust the |
| 321 | * computed dimm capacities accordingly before |
| 322 | * assigning addresses. |
| 323 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 324 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 325 | unsigned int found = 0; |
| 326 | |
| 327 | switch (pinfo->memctl_opts[i].data_bus_width) { |
| 328 | case 2: |
| 329 | /* 16-bit */ |
York Sun | 51d498f | 2011-05-27 07:25:51 +0800 | [diff] [blame] | 330 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 331 | unsigned int dw; |
| 332 | if (!pinfo->dimm_params[i][j].n_ranks) |
| 333 | continue; |
| 334 | dw = pinfo->dimm_params[i][j].primary_sdram_width; |
| 335 | if ((dw == 72 || dw == 64)) { |
| 336 | dbw_cap_adj[i] = 2; |
| 337 | break; |
| 338 | } else if ((dw == 40 || dw == 32)) { |
| 339 | dbw_cap_adj[i] = 1; |
| 340 | break; |
| 341 | } |
| 342 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 343 | break; |
| 344 | |
| 345 | case 1: |
| 346 | /* 32-bit */ |
| 347 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 348 | unsigned int dw; |
| 349 | dw = pinfo->dimm_params[i][j].data_width; |
| 350 | if (pinfo->dimm_params[i][j].n_ranks |
| 351 | && (dw == 72 || dw == 64)) { |
| 352 | /* |
| 353 | * FIXME: can't really do it |
| 354 | * like this because this just |
| 355 | * further reduces the memory |
| 356 | */ |
| 357 | found = 1; |
| 358 | break; |
| 359 | } |
| 360 | } |
| 361 | if (found) { |
| 362 | dbw_cap_adj[i] = 1; |
| 363 | } |
| 364 | break; |
| 365 | |
| 366 | case 0: |
| 367 | /* 64-bit */ |
| 368 | break; |
| 369 | |
| 370 | default: |
| 371 | printf("unexpected data bus width " |
| 372 | "specified controller %u\n", i); |
| 373 | return 1; |
| 374 | } |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 375 | debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 376 | } |
| 377 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 378 | current_mem_base = pinfo->mem_base; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 379 | total_mem = 0; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 380 | if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) { |
| 381 | rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >> |
| 382 | dbw_cap_adj[first_ctrl]; |
| 383 | switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl & |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 384 | FSL_DDR_CS0_CS1_CS2_CS3) { |
| 385 | case FSL_DDR_CS0_CS1_CS2_CS3: |
| 386 | ctlr_density = 4 * rank_density; |
| 387 | break; |
| 388 | case FSL_DDR_CS0_CS1: |
| 389 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: |
| 390 | ctlr_density = 2 * rank_density; |
| 391 | break; |
| 392 | case FSL_DDR_CS2_CS3: |
| 393 | default: |
| 394 | ctlr_density = rank_density; |
| 395 | break; |
| 396 | } |
| 397 | debug("rank density is 0x%llx, ctlr density is 0x%llx\n", |
| 398 | rank_density, ctlr_density); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 399 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 400 | if (pinfo->memctl_opts[i].memctl_interleaving) { |
| 401 | switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { |
York Sun | 6b1e125 | 2014-02-10 13:59:44 -0800 | [diff] [blame] | 402 | case FSL_DDR_256B_INTERLEAVING: |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 403 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 404 | case FSL_DDR_PAGE_INTERLEAVING: |
| 405 | case FSL_DDR_BANK_INTERLEAVING: |
| 406 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
| 407 | total_ctlr_mem = 2 * ctlr_density; |
| 408 | break; |
| 409 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 410 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 411 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 412 | total_ctlr_mem = 3 * ctlr_density; |
| 413 | break; |
| 414 | case FSL_DDR_4WAY_1KB_INTERLEAVING: |
| 415 | case FSL_DDR_4WAY_4KB_INTERLEAVING: |
| 416 | case FSL_DDR_4WAY_8KB_INTERLEAVING: |
| 417 | total_ctlr_mem = 4 * ctlr_density; |
| 418 | break; |
| 419 | default: |
| 420 | panic("Unknown interleaving mode"); |
| 421 | } |
| 422 | pinfo->common_timing_params[i].base_address = |
| 423 | current_mem_base; |
| 424 | pinfo->common_timing_params[i].total_mem = |
| 425 | total_ctlr_mem; |
| 426 | total_mem = current_mem_base + total_ctlr_mem; |
| 427 | debug("ctrl %d base 0x%llx\n", i, current_mem_base); |
| 428 | debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); |
| 429 | } else { |
| 430 | /* when 3rd controller not interleaved */ |
| 431 | current_mem_base = total_mem; |
| 432 | total_ctlr_mem = 0; |
| 433 | pinfo->common_timing_params[i].base_address = |
| 434 | current_mem_base; |
| 435 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 436 | unsigned long long cap = |
| 437 | pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; |
| 438 | pinfo->dimm_params[i][j].base_address = |
| 439 | current_mem_base; |
| 440 | debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); |
| 441 | current_mem_base += cap; |
| 442 | total_ctlr_mem += cap; |
| 443 | } |
| 444 | debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); |
| 445 | pinfo->common_timing_params[i].total_mem = |
| 446 | total_ctlr_mem; |
| 447 | total_mem += total_ctlr_mem; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 448 | } |
| 449 | } |
| 450 | } else { |
| 451 | /* |
| 452 | * Simple linear assignment if memory |
| 453 | * controllers are not interleaved. |
| 454 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 455 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 456 | total_ctlr_mem = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 457 | pinfo->common_timing_params[i].base_address = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 458 | current_mem_base; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 459 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 460 | /* Compute DIMM base addresses. */ |
| 461 | unsigned long long cap = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 462 | pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 463 | pinfo->dimm_params[i][j].base_address = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 464 | current_mem_base; |
| 465 | debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); |
| 466 | current_mem_base += cap; |
| 467 | total_ctlr_mem += cap; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 468 | } |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 469 | debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 470 | pinfo->common_timing_params[i].total_mem = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 471 | total_ctlr_mem; |
| 472 | total_mem += total_ctlr_mem; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 473 | } |
| 474 | } |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 475 | debug("Total mem by %s is 0x%llx\n", __func__, total_mem); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 476 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 477 | return total_mem; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 478 | } |
| 479 | |
York Sun | ef00227 | 2013-03-25 07:39:35 +0000 | [diff] [blame] | 480 | /* Use weak function to allow board file to override the address assignment */ |
| 481 | __attribute__((weak, alias("__step_assign_addresses"))) |
| 482 | unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, |
| 483 | unsigned int dbw_cap_adj[]); |
| 484 | |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 485 | unsigned long long |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 486 | fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
| 487 | unsigned int size_only) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 488 | { |
| 489 | unsigned int i, j; |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 490 | unsigned long long total_mem = 0; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 491 | int assert_reset = 0; |
| 492 | unsigned int first_ctrl = pinfo->first_ctrl; |
| 493 | unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
| 494 | __maybe_unused int retval; |
| 495 | __maybe_unused bool goodspd = false; |
| 496 | __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 497 | |
| 498 | fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; |
| 499 | common_timing_params_t *timing_params = pinfo->common_timing_params; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 500 | if (pinfo->board_need_mem_reset) |
| 501 | assert_reset = pinfo->board_need_mem_reset(); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 502 | |
| 503 | /* data bus width capacity adjust shift amount */ |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 504 | unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS]; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 505 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 506 | for (i = first_ctrl; i <= last_ctrl; i++) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 507 | dbw_capacity_adjust[i] = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 508 | |
| 509 | debug("starting at step %u (%s)\n", |
| 510 | start_step, step_to_string(start_step)); |
| 511 | |
| 512 | switch (start_step) { |
| 513 | case STEP_GET_SPD: |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 514 | #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 515 | /* STEP 1: Gather all DIMM SPD data */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 516 | for (i = first_ctrl; i <= last_ctrl; i++) { |
| 517 | fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i, |
| 518 | dimm_slots_per_ctrl); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | case STEP_COMPUTE_DIMM_PARMS: |
| 522 | /* STEP 2: Compute DIMM parameters from SPD data */ |
| 523 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 524 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 525 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 526 | generic_spd_eeprom_t *spd = |
| 527 | &(pinfo->spd_installed_dimms[i][j]); |
| 528 | dimm_params_t *pdimm = |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 529 | &(pinfo->dimm_params[i][j]); |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 530 | retval = compute_dimm_parameters( |
| 531 | i, spd, pdimm, j); |
York Sun | f2d264b | 2011-06-07 09:42:17 +0800 | [diff] [blame] | 532 | #ifdef CONFIG_SYS_DDR_RAW_TIMING |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 533 | if (!j && retval) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 534 | printf("SPD error on controller %d! " |
| 535 | "Trying fallback to raw timing " |
| 536 | "calculation\n", i); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 537 | retval = fsl_ddr_get_dimm_params(pdimm, |
| 538 | i, j); |
York Sun | f2d264b | 2011-06-07 09:42:17 +0800 | [diff] [blame] | 539 | } |
| 540 | #else |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 541 | if (retval == 2) { |
| 542 | printf("Error: compute_dimm_parameters" |
| 543 | " non-zero returned FATAL value " |
| 544 | "for memctl=%u dimm=%u\n", i, j); |
| 545 | return 0; |
| 546 | } |
York Sun | f2d264b | 2011-06-07 09:42:17 +0800 | [diff] [blame] | 547 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 548 | if (retval) { |
| 549 | debug("Warning: compute_dimm_parameters" |
| 550 | " non-zero return value for memctl=%u " |
| 551 | "dimm=%u\n", i, j); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 552 | } else { |
| 553 | goodspd = true; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 554 | } |
| 555 | } |
| 556 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 557 | if (!goodspd) { |
| 558 | /* |
| 559 | * No valid SPD found |
| 560 | * Throw an error if this is for main memory, i.e. |
| 561 | * first_ctrl == 0. Otherwise, siliently return 0 |
| 562 | * as the memory size. |
| 563 | */ |
| 564 | if (first_ctrl == 0) |
| 565 | printf("Error: No valid SPD detected.\n"); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 566 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 567 | return 0; |
| 568 | } |
Shaohui Xie | 98de369 | 2012-06-28 23:36:38 +0000 | [diff] [blame] | 569 | #elif defined(CONFIG_SYS_DDR_RAW_TIMING) |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 570 | case STEP_COMPUTE_DIMM_PARMS: |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 571 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 572 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 573 | dimm_params_t *pdimm = |
| 574 | &(pinfo->dimm_params[i][j]); |
| 575 | fsl_ddr_get_dimm_params(pdimm, i, j); |
| 576 | } |
| 577 | } |
| 578 | debug("Filling dimm parameters from board specific file\n"); |
| 579 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 580 | case STEP_COMPUTE_COMMON_PARMS: |
| 581 | /* |
| 582 | * STEP 3: Compute a common set of timing parameters |
| 583 | * suitable for all of the DIMMs on each memory controller |
| 584 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 585 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 586 | debug("Computing lowest common DIMM" |
| 587 | " parameters for memctl=%u\n", i); |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 588 | compute_lowest_common_dimm_parameters |
| 589 | (i, |
| 590 | pinfo->dimm_params[i], |
| 591 | &timing_params[i], |
| 592 | CONFIG_DIMM_SLOTS_PER_CTLR); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 593 | } |
| 594 | |
| 595 | case STEP_GATHER_OPTS: |
| 596 | /* STEP 4: Gather configuration requirements from user */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 597 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 598 | debug("Reloading memory controller " |
| 599 | "configuration options for memctl=%u\n", i); |
| 600 | /* |
| 601 | * This "reloads" the memory controller options |
| 602 | * to defaults. If the user "edits" an option, |
| 603 | * next_step points to the step after this, |
| 604 | * which is currently STEP_ASSIGN_ADDRESSES. |
| 605 | */ |
| 606 | populate_memctl_options( |
York Sun | 5684842 | 2015-07-23 14:04:48 -0700 | [diff] [blame] | 607 | &timing_params[i], |
Haiying Wang | dfb4910 | 2008-10-03 12:36:55 -0400 | [diff] [blame] | 608 | &pinfo->memctl_opts[i], |
| 609 | pinfo->dimm_params[i], i); |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 610 | /* |
| 611 | * For RDIMMs, JEDEC spec requires clocks to be stable |
| 612 | * before reset signal is deasserted. For the boards |
| 613 | * using fixed parameters, this function should be |
| 614 | * be called from board init file. |
| 615 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 616 | if (timing_params[i].all_dimms_registered) |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 617 | assert_reset = 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 618 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 619 | if (assert_reset && !size_only) { |
| 620 | if (pinfo->board_mem_reset) { |
| 621 | debug("Asserting mem reset\n"); |
| 622 | pinfo->board_mem_reset(); |
| 623 | } else { |
| 624 | debug("Asserting mem reset missing\n"); |
| 625 | } |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 626 | } |
| 627 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 628 | case STEP_ASSIGN_ADDRESSES: |
| 629 | /* STEP 5: Assign addresses to chip selects */ |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 630 | check_interleaving_options(pinfo); |
| 631 | total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); |
York Sun | 349689b | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 632 | debug("Total mem %llu assigned\n", total_mem); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 633 | |
| 634 | case STEP_COMPUTE_REGS: |
| 635 | /* STEP 6: compute controller register values */ |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 636 | debug("FSL Memory ctrl register computation\n"); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 637 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 638 | if (timing_params[i].ndimms_present == 0) { |
| 639 | memset(&ddr_reg[i], 0, |
| 640 | sizeof(fsl_ddr_cfg_regs_t)); |
| 641 | continue; |
| 642 | } |
| 643 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 644 | compute_fsl_memctl_config_regs |
| 645 | (i, |
| 646 | &pinfo->memctl_opts[i], |
| 647 | &ddr_reg[i], &timing_params[i], |
| 648 | pinfo->dimm_params[i], |
| 649 | dbw_capacity_adjust[i], |
| 650 | size_only); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 651 | } |
| 652 | |
| 653 | default: |
| 654 | break; |
| 655 | } |
| 656 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 657 | { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 658 | /* |
| 659 | * Compute the amount of memory available just by |
| 660 | * looking for the highest valid CSn_BNDS value. |
| 661 | * This allows us to also experiment with using |
| 662 | * only CS0 when using dual-rank DIMMs. |
| 663 | */ |
| 664 | unsigned int max_end = 0; |
| 665 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 666 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 667 | for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { |
| 668 | fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; |
| 669 | if (reg->cs[j].config & 0x80000000) { |
| 670 | unsigned int end; |
York Sun | d8556db | 2013-06-25 11:37:45 -0700 | [diff] [blame] | 671 | /* |
| 672 | * 0xfffffff is a special value we put |
| 673 | * for unused bnds |
| 674 | */ |
| 675 | if (reg->cs[j].bnds == 0xffffffff) |
| 676 | continue; |
| 677 | end = reg->cs[j].bnds & 0xffff; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 678 | if (end > max_end) { |
| 679 | max_end = end; |
| 680 | } |
| 681 | } |
| 682 | } |
| 683 | } |
| 684 | |
York Sun | 00ec3fd | 2013-10-28 16:36:02 -0700 | [diff] [blame] | 685 | total_mem = 1 + (((unsigned long long)max_end << 24ULL) | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 686 | 0xFFFFFFULL) - pinfo->mem_base; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 687 | } |
| 688 | |
| 689 | return total_mem; |
| 690 | } |
| 691 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 692 | phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 693 | { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 694 | unsigned int i, first_ctrl, last_ctrl; |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 695 | #ifdef CONFIG_PPC |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 696 | unsigned int law_memctl = LAW_TRGT_IF_DDR_1; |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 697 | #endif |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 698 | unsigned long long total_memory; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 699 | int deassert_reset = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 700 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 701 | first_ctrl = pinfo->first_ctrl; |
| 702 | last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 703 | |
| 704 | /* Compute it once normally. */ |
York Sun | 6f5e1dc | 2011-09-16 13:21:35 -0700 | [diff] [blame] | 705 | #ifdef CONFIG_FSL_DDR_INTERACTIVE |
James Yang | e8ba6c5 | 2013-01-07 14:01:03 +0000 | [diff] [blame] | 706 | if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 707 | total_memory = fsl_ddr_interactive(pinfo, 0); |
James Yang | e8ba6c5 | 2013-01-07 14:01:03 +0000 | [diff] [blame] | 708 | } else if (fsl_ddr_interactive_env_var_exists()) { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 709 | total_memory = fsl_ddr_interactive(pinfo, 1); |
York Sun | e750cfa | 2013-01-04 08:13:59 +0000 | [diff] [blame] | 710 | } else |
York Sun | 6f5e1dc | 2011-09-16 13:21:35 -0700 | [diff] [blame] | 711 | #endif |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 712 | total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 713 | |
York Sun | f31cfd1 | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 714 | /* setup 3-way interleaving before enabling DDRC */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 715 | switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) { |
| 716 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 717 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 718 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 719 | fsl_ddr_set_intl3r( |
| 720 | pinfo->memctl_opts[first_ctrl]. |
| 721 | memctl_interleaving_mode); |
| 722 | break; |
| 723 | default: |
| 724 | break; |
York Sun | f31cfd1 | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 725 | } |
| 726 | |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 727 | /* |
| 728 | * Program configuration registers. |
| 729 | * JEDEC specs requires clocks to be stable before deasserting reset |
| 730 | * for RDIMMs. Clocks start after chip select is enabled and clock |
| 731 | * control register is set. During step 1, all controllers have their |
| 732 | * registers set but not enabled. Step 2 proceeds after deasserting |
| 733 | * reset through board FPGA or GPIO. |
| 734 | * For non-registered DIMMs, initialization can go through but it is |
| 735 | * also OK to follow the same flow. |
| 736 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 737 | if (pinfo->board_need_mem_reset) |
| 738 | deassert_reset = pinfo->board_need_mem_reset(); |
| 739 | for (i = first_ctrl; i <= last_ctrl; i++) { |
| 740 | if (pinfo->common_timing_params[i].all_dimms_registered) |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 741 | deassert_reset = 1; |
| 742 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 743 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 744 | debug("Programming controller %u\n", i); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 745 | if (pinfo->common_timing_params[i].ndimms_present == 0) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 746 | debug("No dimms present on controller %u; " |
| 747 | "skipping programming\n", i); |
| 748 | continue; |
| 749 | } |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 750 | /* |
| 751 | * The following call with step = 1 returns before enabling |
| 752 | * the controller. It has to finish with step = 2 later. |
| 753 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 754 | fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i, |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 755 | deassert_reset ? 1 : 0); |
| 756 | } |
| 757 | if (deassert_reset) { |
| 758 | /* Use board FPGA or GPIO to deassert reset signal */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 759 | if (pinfo->board_mem_de_reset) { |
| 760 | debug("Deasserting mem reset\n"); |
| 761 | pinfo->board_mem_de_reset(); |
| 762 | } else { |
| 763 | debug("Deasserting mem reset missing\n"); |
| 764 | } |
| 765 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 766 | /* Call with step = 2 to continue initialization */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 767 | fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 768 | i, 2); |
| 769 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 770 | } |
| 771 | |
York Sun | e32d59a | 2015-01-06 13:18:55 -0800 | [diff] [blame] | 772 | #ifdef CONFIG_FSL_DDR_SYNC_REFRESH |
| 773 | fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl); |
| 774 | #endif |
| 775 | |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 776 | #ifdef CONFIG_PPC |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 777 | /* program LAWs */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 778 | for (i = first_ctrl; i <= last_ctrl; i++) { |
| 779 | if (pinfo->memctl_opts[i].memctl_interleaving) { |
| 780 | switch (pinfo->memctl_opts[i]. |
| 781 | memctl_interleaving_mode) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 782 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 783 | case FSL_DDR_PAGE_INTERLEAVING: |
| 784 | case FSL_DDR_BANK_INTERLEAVING: |
| 785 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 786 | if (i % 2) |
| 787 | break; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 788 | if (i == 0) { |
| 789 | law_memctl = LAW_TRGT_IF_DDR_INTRLV; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 790 | fsl_ddr_set_lawbar( |
| 791 | &pinfo->common_timing_params[i], |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 792 | law_memctl, i); |
| 793 | } |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 794 | #if CONFIG_SYS_NUM_DDR_CTLRS > 3 |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 795 | else if (i == 2) { |
| 796 | law_memctl = LAW_TRGT_IF_DDR_INTLV_34; |
| 797 | fsl_ddr_set_lawbar( |
| 798 | &pinfo->common_timing_params[i], |
| 799 | law_memctl, i); |
| 800 | } |
| 801 | #endif |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 802 | break; |
| 803 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 804 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 805 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 806 | law_memctl = LAW_TRGT_IF_DDR_INTLV_123; |
| 807 | if (i == 0) { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 808 | fsl_ddr_set_lawbar( |
| 809 | &pinfo->common_timing_params[i], |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 810 | law_memctl, i); |
| 811 | } |
| 812 | break; |
| 813 | case FSL_DDR_4WAY_1KB_INTERLEAVING: |
| 814 | case FSL_DDR_4WAY_4KB_INTERLEAVING: |
| 815 | case FSL_DDR_4WAY_8KB_INTERLEAVING: |
| 816 | law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; |
| 817 | if (i == 0) |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 818 | fsl_ddr_set_lawbar( |
| 819 | &pinfo->common_timing_params[i], |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 820 | law_memctl, i); |
| 821 | /* place holder for future 4-way interleaving */ |
| 822 | break; |
| 823 | default: |
| 824 | break; |
| 825 | } |
| 826 | } else { |
| 827 | switch (i) { |
| 828 | case 0: |
| 829 | law_memctl = LAW_TRGT_IF_DDR_1; |
| 830 | break; |
| 831 | case 1: |
| 832 | law_memctl = LAW_TRGT_IF_DDR_2; |
| 833 | break; |
| 834 | case 2: |
| 835 | law_memctl = LAW_TRGT_IF_DDR_3; |
| 836 | break; |
| 837 | case 3: |
| 838 | law_memctl = LAW_TRGT_IF_DDR_4; |
| 839 | break; |
| 840 | default: |
| 841 | break; |
| 842 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 843 | fsl_ddr_set_lawbar(&pinfo->common_timing_params[i], |
| 844 | law_memctl, i); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 845 | } |
| 846 | } |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 847 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 848 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 849 | debug("total_memory by %s = %llu\n", __func__, total_memory); |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 850 | |
| 851 | #if !defined(CONFIG_PHYS_64BIT) |
| 852 | /* Check for 4G or more. Bad. */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 853 | if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) { |
Shruti Kanetkar | 2f848f9 | 2013-08-15 11:25:37 -0500 | [diff] [blame] | 854 | puts("Detected "); |
| 855 | print_size(total_memory, " of memory\n"); |
Becky Bruce | 7ea3871 | 2010-12-17 17:17:59 -0600 | [diff] [blame] | 856 | printf(" This U-Boot only supports < 4G of DDR\n"); |
| 857 | printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); |
Simon Glass | f1683aa | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 858 | printf(" "); /* re-align to match init_dram print */ |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 859 | total_memory = CONFIG_MAX_MEM_MAPPED; |
| 860 | } |
| 861 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 862 | |
| 863 | return total_memory; |
| 864 | } |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 865 | |
| 866 | /* |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 867 | * fsl_ddr_sdram(void) -- this is the main function to be |
Simon Glass | f1683aa | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 868 | * called by dram_init() in the board file. |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 869 | * |
| 870 | * It returns amount of memory configured in bytes. |
| 871 | */ |
| 872 | phys_size_t fsl_ddr_sdram(void) |
| 873 | { |
| 874 | fsl_ddr_info_t info; |
| 875 | |
| 876 | /* Reset info structure. */ |
| 877 | memset(&info, 0, sizeof(fsl_ddr_info_t)); |
| 878 | info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
| 879 | info.first_ctrl = 0; |
| 880 | info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; |
| 881 | info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |
| 882 | info.board_need_mem_reset = board_need_mem_reset; |
| 883 | info.board_mem_reset = board_assert_mem_reset; |
| 884 | info.board_mem_de_reset = board_deassert_mem_reset; |
York Sun | 61bd2f7 | 2015-11-04 09:53:10 -0800 | [diff] [blame] | 885 | remove_unused_controllers(&info); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 886 | |
| 887 | return __fsl_ddr_sdram(&info); |
| 888 | } |
| 889 | |
| 890 | #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
| 891 | phys_size_t fsl_other_ddr_sdram(unsigned long long base, |
| 892 | unsigned int first_ctrl, |
| 893 | unsigned int num_ctrls, |
| 894 | unsigned int dimm_slots_per_ctrl, |
| 895 | int (*board_need_reset)(void), |
| 896 | void (*board_reset)(void), |
| 897 | void (*board_de_reset)(void)) |
| 898 | { |
| 899 | fsl_ddr_info_t info; |
| 900 | |
| 901 | /* Reset info structure. */ |
| 902 | memset(&info, 0, sizeof(fsl_ddr_info_t)); |
| 903 | info.mem_base = base; |
| 904 | info.first_ctrl = first_ctrl; |
| 905 | info.num_ctrls = num_ctrls; |
| 906 | info.dimm_slots_per_ctrl = dimm_slots_per_ctrl; |
| 907 | info.board_need_mem_reset = board_need_reset; |
| 908 | info.board_mem_reset = board_reset; |
| 909 | info.board_mem_de_reset = board_de_reset; |
| 910 | |
| 911 | return __fsl_ddr_sdram(&info); |
| 912 | } |
| 913 | #endif |
| 914 | |
| 915 | /* |
| 916 | * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the |
| 917 | * size of the total memory without setting ddr control registers. |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 918 | */ |
| 919 | phys_size_t |
| 920 | fsl_ddr_sdram_size(void) |
| 921 | { |
| 922 | fsl_ddr_info_t info; |
| 923 | unsigned long long total_memory = 0; |
| 924 | |
| 925 | memset(&info, 0 , sizeof(fsl_ddr_info_t)); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 926 | info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
| 927 | info.first_ctrl = 0; |
| 928 | info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; |
| 929 | info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |
| 930 | info.board_need_mem_reset = NULL; |
Ed Swarthout | 81dfdee | 2016-01-14 12:28:04 -0600 | [diff] [blame] | 931 | remove_unused_controllers(&info); |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 932 | |
| 933 | /* Compute it once normally. */ |
| 934 | total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); |
| 935 | |
| 936 | return total_memory; |
| 937 | } |