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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Philipp Tomsich1168d2d2017-07-28 17:43:19 +02002/*
3 * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
Philipp Tomsich1168d2d2017-07-28 17:43:19 +02004 */
5
6#include <common.h>
Simon Glass52f24232020-05-10 11:40:00 -06007#include <bootstage.h>
Philipp Tomsich1168d2d2017-07-28 17:43:19 +02008#include <dm.h>
Simon Glass691d7192020-05-10 11:40:02 -06009#include <init.h>
Philipp Tomsichcc7ce942017-09-11 22:04:16 +020010#include <dm/ofnode.h>
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020011#include <mapmem.h>
Kever Yang15f09a12019-03-28 11:01:23 +080012#include <asm/arch-rockchip/timer.h>
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020013#include <dt-structs.h>
14#include <timer.h>
15#include <asm/io.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19#if CONFIG_IS_ENABLED(OF_PLATDATA)
20struct rockchip_timer_plat {
21 struct dtd_rockchip_rk3368_timer dtd;
22};
23#endif
24
25/* Driver private data. Contains timer id. Could be either 0 or 1. */
26struct rockchip_timer_priv {
27 struct rk_timer *timer;
28};
29
Philipp Tomsichcc7ce942017-09-11 22:04:16 +020030static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer)
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020031{
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020032 uint64_t timebase_h, timebase_l;
33 uint64_t cntr;
34
Philipp Tomsichcc7ce942017-09-11 22:04:16 +020035 timebase_l = readl(&timer->timer_curr_value0);
36 timebase_h = readl(&timer->timer_curr_value1);
37
38 cntr = timebase_h << 32 | timebase_l;
39 return cntr;
40}
41
42#if CONFIG_IS_ENABLED(BOOTSTAGE)
43ulong timer_get_boot_us(void)
44{
45 uint64_t ticks = 0;
46 uint32_t rate;
47 uint64_t us;
48 int ret;
49
50 ret = dm_timer_init();
51
52 if (!ret) {
53 /* The timer is available */
54 rate = timer_get_rate(gd->timer);
55 timer_get_count(gd->timer, &ticks);
56#if !CONFIG_IS_ENABLED(OF_PLATDATA)
57 } else if (ret == -EAGAIN) {
58 /* We have been called so early that the DM is not ready,... */
59 ofnode node = offset_to_ofnode(-1);
60 struct rk_timer *timer = NULL;
61
62 /*
63 * ... so we try to access the raw timer, if it is specified
64 * via the tick-timer property in /chosen.
65 */
66 node = ofnode_get_chosen_node("tick-timer");
67 if (!ofnode_valid(node)) {
68 debug("%s: no /chosen/tick-timer\n", __func__);
69 return 0;
70 }
71
72 timer = (struct rk_timer *)ofnode_get_addr(node);
73
74 /* This timer is down-counting */
75 ticks = ~0uLL - rockchip_timer_get_curr_value(timer);
76 if (ofnode_read_u32(node, "clock-frequency", &rate)) {
77 debug("%s: could not read clock-frequency\n", __func__);
78 return 0;
79 }
80#endif
81 } else {
82 return 0;
83 }
84
85 us = (ticks * 1000) / rate;
86 return us;
87}
88#endif
89
90static int rockchip_timer_get_count(struct udevice *dev, u64 *count)
91{
92 struct rockchip_timer_priv *priv = dev_get_priv(dev);
93 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer);
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020094
95 /* timers are down-counting */
Philipp Tomsich1168d2d2017-07-28 17:43:19 +020096 *count = ~0ull - cntr;
97 return 0;
98}
99
100static int rockchip_clk_ofdata_to_platdata(struct udevice *dev)
101{
102#if !CONFIG_IS_ENABLED(OF_PLATDATA)
103 struct rockchip_timer_priv *priv = dev_get_priv(dev);
104
Philipp Tomsich6675c952017-09-11 22:04:17 +0200105 priv->timer = dev_read_addr_ptr(dev);
106 if (!priv->timer)
107 return -ENOENT;
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200108#endif
109
110 return 0;
111}
112
113static int rockchip_timer_start(struct udevice *dev)
114{
115 struct rockchip_timer_priv *priv = dev_get_priv(dev);
116 const uint64_t reload_val = ~0uLL;
117 const uint32_t reload_val_l = reload_val & 0xffffffff;
118 const uint32_t reload_val_h = reload_val >> 32;
119
Philipp Tomsichcc7ce942017-09-11 22:04:16 +0200120 /* don't reinit, if the timer is already running and set up */
121 if ((readl(&priv->timer->timer_ctrl_reg) & 1) == 1 &&
122 (readl(&priv->timer->timer_load_count0) == reload_val_l) &&
123 (readl(&priv->timer->timer_load_count1) == reload_val_h))
124 return 0;
125
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200126 /* disable timer and reset all control */
127 writel(0, &priv->timer->timer_ctrl_reg);
128 /* write reload value */
129 writel(reload_val_l, &priv->timer->timer_load_count0);
130 writel(reload_val_h, &priv->timer->timer_load_count1);
131 /* enable timer */
132 writel(1, &priv->timer->timer_ctrl_reg);
133
134 return 0;
135}
136
137static int rockchip_timer_probe(struct udevice *dev)
138{
139#if CONFIG_IS_ENABLED(OF_PLATDATA)
140 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
141 struct rockchip_timer_priv *priv = dev_get_priv(dev);
142 struct rockchip_timer_plat *plat = dev_get_platdata(dev);
143
Philipp Tomsich8158a842017-08-14 19:05:31 +0200144 priv->timer = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200145 uc_priv->clock_rate = plat->dtd.clock_frequency;
146#endif
147
148 return rockchip_timer_start(dev);
149}
150
151static const struct timer_ops rockchip_timer_ops = {
152 .get_count = rockchip_timer_get_count,
153};
154
155static const struct udevice_id rockchip_timer_ids[] = {
Philipp Tomsiche0e1d3f2018-04-25 14:07:06 +0200156 { .compatible = "rockchip,rk3188-timer" },
157 { .compatible = "rockchip,rk3288-timer" },
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200158 { .compatible = "rockchip,rk3368-timer" },
159 {}
160};
161
Philipp Tomsich5798d502017-08-25 13:22:00 +0200162U_BOOT_DRIVER(rockchip_rk3368_timer) = {
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200163 .name = "rockchip_rk3368_timer",
164 .id = UCLASS_TIMER,
165 .of_match = rockchip_timer_ids,
166 .probe = rockchip_timer_probe,
167 .ops = &rockchip_timer_ops,
Philipp Tomsich1168d2d2017-07-28 17:43:19 +0200168 .priv_auto_alloc_size = sizeof(struct rockchip_timer_priv),
169#if CONFIG_IS_ENABLED(OF_PLATDATA)
170 .platdata_auto_alloc_size = sizeof(struct rockchip_timer_plat),
171#endif
172 .ofdata_to_platdata = rockchip_clk_ofdata_to_platdata,
173};