blob: 100350d7a1bbd5735a8c5096d88ab35b9556c273 [file] [log] [blame]
Daniel Hellstrom69403832008-03-26 23:34:47 +01001/* Linker script for Gaisler Research AB's Template design
2 * for Altera NIOS Development board Stratix II Edition, EP2S60 FPGA.
3 *
4 * (C) Copyright 2008
5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 */
26
27OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc")
28OUTPUT_ARCH(sparc)
29ENTRY(_start)
30SECTIONS
31{
32
33/* Read-only sections, merged into text segment: */
34 . = + SIZEOF_HEADERS;
35 .interp : { *(.interp) }
36 .hash : { *(.hash) }
37 .dynsym : { *(.dynsym) }
38 .dynstr : { *(.dynstr) }
39 .rel.text : { *(.rel.text) }
40 .rela.text : { *(.rela.text) }
41 .rel.data : { *(.rel.data) }
42 .rela.data : { *(.rela.data) }
43 .rel.rodata : { *(.rel.rodata) }
44 .rela.rodata : { *(.rela.rodata) }
45 .rel.got : { *(.rel.got) }
46 .rela.got : { *(.rela.got) }
47 .rel.ctors : { *(.rel.ctors) }
48 .rela.ctors : { *(.rela.ctors) }
49 .rel.dtors : { *(.rel.dtors) }
50 .rela.dtors : { *(.rela.dtors) }
51 .rel.bss : { *(.rel.bss) }
52 .rela.bss : { *(.rela.bss) }
53 .rel.plt : { *(.rel.plt) }
54 .rela.plt : { *(.rela.plt) }
55 .init : { *(.init) }
56 .plt : { *(.plt) }
57
58 .text : {
59 _load_addr = .;
60 _text = .;
61
62 *(.start)
63 cpu/leon3/start.o (.text)
64/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */
65 . = ALIGN(8192);
66/* PROM CODE, Will be relocated to the end of memory,
67 * no global data accesses please.
68 */
69 __prom_start = .;
70 *(.prom.pgt)
71 *(.prom.data)
72 *(.prom.text)
73 . = ALIGN(16);
74 __prom_end = .;
75 *(.text)
76 *(.fixup)
77 *(.gnu.warning)
78/* *(.got1)*/
79 . = ALIGN(16);
80 *(.rodata)
81 *(.rodata1)
82 *(.rodata.*)
83 *(.eh_frame)
84 }
85 . = ALIGN(4);
86 _etext = .;
87
88 /* CMD Table */
89
90 __u_boot_cmd_start = .;
91 .u_boot_cmd : { *(.u_boot_cmd) }
92 . = ALIGN(4);
93 __u_boot_cmd_end = .;
94
95 .data :
96 {
97 *(.data)
98 *(.data1)
99 *(.data.rel)
100 *(.data.rel.*)
101 *(.sdata)
102 *(.sdata2)
103 *(.dynamic)
104 CONSTRUCTORS
105 }
106 _edata = .;
107 PROVIDE (edata = .);
108
109 . = ALIGN(4);
110 __got_start = .;
111 .got : {
112 *(.got)
113/* *(.data.rel)
114 *(.data.rel.local)*/
115 . = ALIGN(16);
116 }
117 __got_end = .;
118
119/* .data.rel : { } */
120
121 . = ALIGN(4096);
122 __init_begin = .;
123 .text.init : { *(.text.init) }
124 .data.init : { *(.data.init) }
125 . = ALIGN(4096);
126 __init_end = .;
127
128 __bss_start = .;
129 .bss :
130 {
131 *(.sbss) *(.scommon)
132 *(.dynbss)
133 *(.bss)
134 *(COMMON)
135 . = ALIGN(16); /* to speed clearing of bss up */
136 }
137 __bss_end = . ;
138 _end = . ;
139 PROVIDE (end = .);
140
141/* Relocated into main memory */
142
143 /* Start of main memory */
144 /*. = 0x40000000;*/
145
146 .stack (NOLOAD) : { *(.stack) }
147
148 /* PROM CODE */
149
150 /* global data in RAM passed to kernel after booting */
151
152 .stab 0 : { *(.stab) }
153 .stabstr 0 : { *(.stabstr) }
154 .stab.excl 0 : { *(.stab.excl) }
155 .stab.exclstr 0 : { *(.stab.exclstr) }
156 .stab.index 0 : { *(.stab.index) }
157 .stab.indexstr 0 : { *(.stab.indexstr) }
158 .comment 0 : { *(.comment) }
159
160}