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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------
2 . smc91111.c
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4 .
5 . (C) Copyright 2002
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
8 .
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
12 .
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
17 .
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
22 .
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 .
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
30 .
31 .
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
37 .
38 . Arguments:
39 . io = for the base address
40 . irq = for the IRQ
41 .
42 . author:
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
45 .
46 .
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
48 .
49 . Sources:
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
53 .
54 . History:
55 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
56 . 07/25/01 Woojung Huh Modify for ADS Bitsy
57 . 04/25/01 Daris A Nevil Initial public release through SMSC
58 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
59 ----------------------------------------------------------------------------*/
60
61#include <common.h>
62#include <command.h>
63#include "smc91111.h"
64#include <net.h>
65
66#ifdef CONFIG_DRIVER_SMC91111
67
68/* Use power-down feature of the chip */
69#define POWER_DOWN 0
70
71#define NO_AUTOPROBE
72
73static const char version[] =
74 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
75
76#define SMC_DEBUG 0
77
78/*------------------------------------------------------------------------
79 .
80 . Configuration options, for the experienced user to change.
81 .
82 -------------------------------------------------------------------------*/
83
84/*
85 . Wait time for memory to be free. This probably shouldn't be
86 . tuned that much, as waiting for this means nothing else happens
87 . in the system
88*/
89#define MEMORY_WAIT_TIME 16
90
91
92#if (SMC_DEBUG > 2 )
93#define PRINTK3(args...) printf(args)
94#else
95#define PRINTK3(args...)
96#endif
97
98#if SMC_DEBUG > 1
99#define PRINTK2(args...) printf(args)
100#else
101#define PRINTK2(args...)
102#endif
103
104#ifdef SMC_DEBUG
105#define PRINTK(args...) printf(args)
106#else
107#define PRINTK(args...)
108#endif
109
110
111/*------------------------------------------------------------------------
112 .
113 . The internal workings of the driver. If you are changing anything
114 . here with the SMC stuff, you should have the datasheet and know
115 . what you are doing.
116 .
117 -------------------------------------------------------------------------*/
118#define CARDNAME "LAN91C111"
119
120/* Memory sizing constant */
121#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
122
123#ifndef CONFIG_SMC91111_BASE
124#define CONFIG_SMC91111_BASE 0x20000300
125#endif
126
127#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
128
129#define SMC_DEV_NAME "SMC91111"
130#define SMC_PHY_ADDR 0x0000
131#define SMC_ALLOC_MAX_TRY 5
132#define SMC_TX_TIMEOUT 30
133
134#define SMC_PHY_CLOCK_DELAY 1000
135
136#define ETH_ZLEN 60
137
138#ifdef CONFIG_SMC_USE_32_BIT
139#define USE_32_BIT 1
140#else
141#undef USE_32_BIT
142#endif
143/*-----------------------------------------------------------------
144 .
145 . The driver can be entered at any of the following entry points.
146 .
147 .------------------------------------------------------------------ */
148
149extern int eth_init(bd_t *bd);
150extern void eth_halt(void);
151extern int eth_rx(void);
152extern int eth_send(volatile void *packet, int length);
153
154
155
156
157
158/*
159 . This is called by register_netdev(). It is responsible for
160 . checking the portlist for the SMC9000 series chipset. If it finds
161 . one, then it will initialize the device, find the hardware information,
162 . and sets up the appropriate device parameters.
163 . NOTE: Interrupts are *OFF* when this procedure is called.
164 .
165 . NB:This shouldn't be static since it is referred to externally.
166*/
167int smc_init(void);
168
169/*
170 . This is called by unregister_netdev(). It is responsible for
171 . cleaning up before the driver is finally unregistered and discarded.
172*/
173void smc_destructor(void);
174
175/*
176 . The kernel calls this function when someone wants to use the device,
177 . typically 'ifconfig ethX up'.
178*/
179static int smc_open(void);
180
181
182/*
183 . This is called by the kernel in response to 'ifconfig ethX down'. It
184 . is responsible for cleaning up everything that the open routine
185 . does, and maybe putting the card into a powerdown state.
186*/
187static int smc_close(void);
188
189/*
190 . Configures the PHY through the MII Management interface
191*/
192#ifndef CONFIG_SMC91111_EXT_PHY
193static void smc_phy_configure(void);
194#endif /* !CONFIG_SMC91111_EXT_PHY */
195
196/*
197 . This is a separate procedure to handle the receipt of a packet, to
198 . leave the interrupt code looking slightly cleaner
199*/
200static int smc_rcv(void);
201
202
203
204/*
205 ------------------------------------------------------------
206 .
207 . Internal routines
208 .
209 ------------------------------------------------------------
210*/
211
212static char smc_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
213
214/*
215 * This function must be called before smc_open() if you want to override
216 * the default mac address.
217 */
218
219void smc_set_mac_addr(const char *addr) {
220 int i;
221
222 for (i=0; i < sizeof(smc_mac_addr); i++){
223 smc_mac_addr[i] = addr[i];
224 }
225}
226
227/*
228 * smc_get_macaddr is no longer used. If you want to override the default
229 * mac address, call smc_get_mac_addr as a part of the board initialisation.
230 */
231
232#if 0
233void smc_get_macaddr( byte *addr ) {
234 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
235 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
236 int i;
237
238
239 for (i=0; i<6; i++) {
240 addr[0] = *(dnp1110_mac+0);
241 addr[1] = *(dnp1110_mac+1);
242 addr[2] = *(dnp1110_mac+2);
243 addr[3] = *(dnp1110_mac+3);
244 addr[4] = *(dnp1110_mac+4);
245 addr[5] = *(dnp1110_mac+5);
246 }
247}
248#endif /* 0 */
249
250/***********************************************
251 * Show available memory *
252 ***********************************************/
253void dump_memory_info(void)
254{
255 word mem_info;
256 word old_bank;
257
258 old_bank = SMC_inw(BANK_SELECT)&0xF;
259
260 SMC_SELECT_BANK(0);
261 mem_info = SMC_inw( MIR_REG );
262 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
263
264 SMC_SELECT_BANK(old_bank);
265}
266/*
267 . A rather simple routine to print out a packet for debugging purposes.
268*/
269#if SMC_DEBUG > 2
270static void print_packet( byte *, int );
271#endif
272
273#define tx_done(dev) 1
274
275
276
277/* this does a soft reset on the device */
278static void smc_reset( void );
279
280/* Enable Interrupts, Receive, and Transmit */
281static void smc_enable( void );
282
283/* this puts the device in an inactive state */
284static void smc_shutdown( void );
285
286/* Routines to Read and Write the PHY Registers across the
287 MII Management Interface
288*/
289
290#ifndef CONFIG_SMC91111_EXT_PHY
291static word smc_read_phy_register(byte phyreg);
292static void smc_write_phy_register(byte phyreg, word phydata);
293#endif /* !CONFIG_SMC91111_EXT_PHY */
294
295
296static int poll4int( byte mask, int timeout ) {
297 int tmo = get_timer(0) + timeout * CFG_HZ;
298 int is_timeout = 0;
299 word old_bank = SMC_inw(BSR_REG);
300
301 PRINTK2("Polling...\n");
302 SMC_SELECT_BANK(2);
303 while((SMC_inw(SMC91111_INT_REG) & mask) == 0)
304 {
305 if (get_timer(0) >= tmo) {
306 is_timeout = 1;
307 break;
308 }
309 }
310
311 /* restore old bank selection */
312 SMC_SELECT_BANK(old_bank);
313
314 if (is_timeout)
315 return 1;
316 else
317 return 0;
318}
319
320/*
321 . Function: smc_reset( void )
322 . Purpose:
323 . This sets the SMC91111 chip to its normal state, hopefully from whatever
324 . mess that any other DOS driver has put it in.
325 .
326 . Maybe I should reset more registers to defaults in here? SOFTRST should
327 . do that for me.
328 .
329 . Method:
330 . 1. send a SOFT RESET
331 . 2. wait for it to finish
332 . 3. enable autorelease mode
333 . 4. reset the memory management unit
334 . 5. clear all interrupts
335 .
336*/
337static void smc_reset( void )
338{
339 PRINTK2("%s:smc_reset\n", SMC_DEV_NAME);
340
341 /* This resets the registers mostly to defaults, but doesn't
342 affect EEPROM. That seems unnecessary */
343 SMC_SELECT_BANK( 0 );
344 SMC_outw( RCR_SOFTRST, RCR_REG );
345
346 /* Setup the Configuration Register */
347 /* This is necessary because the CONFIG_REG is not affected */
348 /* by a soft reset */
349
350 SMC_SELECT_BANK( 1 );
351#if defined(CONFIG_SMC91111_EXT_PHY)
352 SMC_outw( CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
353#else
354 SMC_outw( CONFIG_DEFAULT, CONFIG_REG);
355#endif
356
357
358 /* Release from possible power-down state */
359 /* Configuration register is not affected by Soft Reset */
360 SMC_outw( SMC_inw( CONFIG_REG ) | CONFIG_EPH_POWER_EN, CONFIG_REG );
361
362 SMC_SELECT_BANK( 0 );
363
364 /* this should pause enough for the chip to be happy */
365 udelay(10);
366
367 /* Disable transmit and receive functionality */
368 SMC_outw( RCR_CLEAR, RCR_REG );
369 SMC_outw( TCR_CLEAR, TCR_REG );
370
371 /* set the control register */
372 SMC_SELECT_BANK( 1 );
373 SMC_outw( CTL_DEFAULT, CTL_REG );
374
375 /* Reset the MMU */
376 SMC_SELECT_BANK( 2 );
377 SMC_outw( MC_RESET, MMU_CMD_REG );
378 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
379 udelay(1); /* Wait until not busy */
380
381 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
382 but this is a place where future chipsets _COULD_ break. Be wary
383 of issuing another MMU command right after this */
384
385 /* Disable all interrupts */
386 SMC_outb( 0, IM_REG );
387}
388
389/*
390 . Function: smc_enable
391 . Purpose: let the chip talk to the outside work
392 . Method:
393 . 1. Enable the transmitter
394 . 2. Enable the receiver
395 . 3. Enable interrupts
396*/
397static void smc_enable()
398{
399 PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
400 SMC_SELECT_BANK( 0 );
401 /* see the header file for options in TCR/RCR DEFAULT*/
402 SMC_outw( TCR_DEFAULT, TCR_REG );
403 SMC_outw( RCR_DEFAULT, RCR_REG );
404
405 /* clear MII_DIS */
406/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
407}
408
409/*
410 . Function: smc_shutdown
411 . Purpose: closes down the SMC91xxx chip.
412 . Method:
413 . 1. zero the interrupt mask
414 . 2. clear the enable receive flag
415 . 3. clear the enable xmit flags
416 .
417 . TODO:
418 . (1) maybe utilize power down mode.
419 . Why not yet? Because while the chip will go into power down mode,
420 . the manual says that it will wake up in response to any I/O requests
421 . in the register space. Empirical results do not show this working.
422*/
423static void smc_shutdown()
424{
425 PRINTK2(CARDNAME ":smc_shutdown\n");
426
427 /* no more interrupts for me */
428 SMC_SELECT_BANK( 2 );
429 SMC_outb( 0, IM_REG );
430
431 /* and tell the card to stay away from that nasty outside world */
432 SMC_SELECT_BANK( 0 );
433 SMC_outb( RCR_CLEAR, RCR_REG );
434 SMC_outb( TCR_CLEAR, TCR_REG );
435}
436
437
438/*
439 . Function: smc_hardware_send_packet(struct net_device * )
440 . Purpose:
441 . This sends the actual packet to the SMC9xxx chip.
442 .
443 . Algorithm:
444 . First, see if a saved_skb is available.
445 . ( this should NOT be called if there is no 'saved_skb'
446 . Now, find the packet number that the chip allocated
447 . Point the data pointers at it in memory
448 . Set the length word in the chip's memory
449 . Dump the packet to chip memory
450 . Check if a last byte is needed ( odd length packet )
451 . if so, set the control flag right
452 . Tell the card to send it
453 . Enable the transmit interrupt, so I know if it failed
454 . Free the kernel data if I actually sent it.
455*/
456static int smc_send_packet(volatile void *packet, int packet_length)
457{
458 byte packet_no;
459 unsigned long ioaddr;
460 byte * buf;
461 int length;
462 int numPages;
463 int try = 0;
464 int time_out;
465 byte status;
466
467
468 PRINTK3("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
469
470 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
471
472 /* allocate memory
473 ** The MMU wants the number of pages to be the number of 256 bytes
474 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
475 **
476 ** The 91C111 ignores the size bits, but the code is left intact
477 ** for backwards and future compatibility.
478 **
479 ** Pkt size for allocating is data length +6 (for additional status
480 ** words, length and ctl!)
481 **
482 ** If odd size then last byte is included in this header.
483 */
484 numPages = ((length & 0xfffe) + 6);
485 numPages >>= 8; /* Divide by 256 */
486
487 if (numPages > 7 ) {
488 printf("%s: Far too big packet error. \n", SMC_DEV_NAME);
489 return 0;
490 }
491
492 /* now, try to allocate the memory */
493 SMC_SELECT_BANK( 2 );
494 SMC_outw( MC_ALLOC | numPages, MMU_CMD_REG );
495
496again:
497 try++;
498 time_out = MEMORY_WAIT_TIME;
499 do {
500 status = SMC_inb( SMC91111_INT_REG );
501 if ( status & IM_ALLOC_INT ) {
502 /* acknowledge the interrupt */
503 SMC_outb( IM_ALLOC_INT, SMC91111_INT_REG );
504 break;
505 }
506 } while ( -- time_out );
507
508 if ( !time_out ) {
509 PRINTK2("%s: memory allocation, try %d failed ...\n",
510 SMC_DEV_NAME, try);
511 if (try < SMC_ALLOC_MAX_TRY)
512 goto again;
513 else
514 return 0;
515 }
516
517 PRINTK2("%s: memory allocation, try %d succeeded ...\n",
518 SMC_DEV_NAME,
519 try);
520
521 /* I can send the packet now.. */
522
523 ioaddr = SMC_BASE_ADDRESS;
524
525 buf = (byte *)packet;
526
527 /* If I get here, I _know_ there is a packet slot waiting for me */
528 packet_no = SMC_inb( AR_REG );
529 if ( packet_no & AR_FAILED ) {
530 /* or isn't there? BAD CHIP! */
531 printf("%s: Memory allocation failed. \n",
532 SMC_DEV_NAME);
533 return 0;
534 }
535
536 /* we have a packet address, so tell the card to use it */
537 SMC_outb( packet_no, PN_REG );
538
539 /* point to the beginning of the packet */
540 SMC_outw( PTR_AUTOINC , PTR_REG );
541
542 PRINTK3("%s: Trying to xmit packet of length %x\n",
543 SMC_DEV_NAME, length);
544
545#if SMC_DEBUG > 2
546 printf("Transmitting Packet\n");
547 print_packet( buf, length );
548#endif
549
550 /* send the packet length ( +6 for status, length and ctl byte )
551 and the status word ( set to zeros ) */
552#ifdef USE_32_BIT
553 SMC_outl( (length +6 ) << 16 , SMC91111_DATA_REG );
554#else
555 SMC_outw( 0, SMC91111_DATA_REG );
556 /* send the packet length ( +6 for status words, length, and ctl*/
557 SMC_outw( (length+6), SMC91111_DATA_REG );
558#endif
559
560 /* send the actual data
561 . I _think_ it's faster to send the longs first, and then
562 . mop up by sending the last word. It depends heavily
563 . on alignment, at least on the 486. Maybe it would be
564 . a good idea to check which is optimal? But that could take
565 . almost as much time as is saved?
566 */
567#ifdef USE_32_BIT
568 SMC_outsl(SMC91111_DATA_REG, buf, length >> 2 );
569 if ( length & 0x2 )
570 SMC_outw(*((word *)(buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG);
571#else
572 SMC_outsw(SMC91111_DATA_REG , buf, (length ) >> 1);
573#endif /* USE_32_BIT */
574
575 /* Send the last byte, if there is one. */
576 if ( (length & 1) == 0 ) {
577 SMC_outw( 0, SMC91111_DATA_REG );
578 } else {
579 SMC_outw( buf[length -1 ] | 0x2000, SMC91111_DATA_REG );
580 }
581
582 /* and let the chipset deal with it */
583 SMC_outw( MC_ENQUEUE , MMU_CMD_REG );
584
585 /* poll for TX INT */
586 if (poll4int(IM_TX_INT, SMC_TX_TIMEOUT)) {
587 /* sending failed */
588 PRINTK2("%s: TX timeout, sending failed...\n",
589 SMC_DEV_NAME);
590
591 /* release packet */
592 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
593
594 /* wait for MMU getting ready (low) */
595 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
596 {
597 udelay(10);
598 }
599
600 PRINTK2("MMU ready\n");
601
602
603 return 0;
604 } else {
605 /* ack. int */
606 SMC_outw(IM_TX_INT, SMC91111_INT_REG);
607 PRINTK2("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
608
609 /* release packet */
610 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
611
612 /* wait for MMU getting ready (low) */
613 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
614 {
615 udelay(10);
616 }
617
618 PRINTK2("MMU ready\n");
619
620
621 }
622
623 return length;
624}
625
626/*-------------------------------------------------------------------------
627 |
628 | smc_destructor( struct net_device * dev )
629 | Input parameters:
630 | dev, pointer to the device structure
631 |
632 | Output:
633 | None.
634 |
635 ---------------------------------------------------------------------------
636*/
637void smc_destructor()
638{
639 PRINTK2(CARDNAME ":smc_destructor\n");
640}
641
642
643/*
644 * Open and Initialize the board
645 *
646 * Set up everything, reset the card, etc ..
647 *
648 */
649static int smc_open()
650{
651 int i; /* used to set hw ethernet address */
652
653 PRINTK2("%s:smc_open\n", SMC_DEV_NAME);
654
655 /* reset the hardware */
656
657 smc_reset();
658 smc_enable();
659
660 /* Configure the PHY */
661#ifndef CONFIG_SMC91111_EXT_PHY
662 smc_phy_configure();
663#endif
664
665
666 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
667/* SMC_SELECT_BANK(0); */
668/* SMC_outw(0, RPC_REG); */
669
670#ifdef USE_32_BIT
671 for ( i = 0; i < 6; i += 2 ) {
672 word address;
673
674 address = smc_mac_addr[ i + 1 ] << 8 ;
675 address |= smc_mac_addr[ i ];
676 SMC_outw( address, ADDR0_REG + i );
677 }
678#else
679 for ( i = 0; i < 6; i ++ )
680 SMC_outb( smc_mac_addr[i], ADDR0_REG + i );
681#endif
682
683 return 0;
684}
685
686#if 0 /* dead code? -- wd */
687#ifdef USE_32_BIT
688void
689insl32(r,b,l)
690{
691 int __i ;
692 dword *__b2;
693
694 __b2 = (dword *) b;
695 for (__i = 0; __i < l; __i++) {
696 *(__b2 + __i) = *(dword *)(r+0x10000300);
697 }
698}
699#endif
700#endif
701
702/*-------------------------------------------------------------
703 .
704 . smc_rcv - receive a packet from the card
705 .
706 . There is ( at least ) a packet waiting to be read from
707 . chip-memory.
708 .
709 . o Read the status
710 . o If an error, record it
711 . o otherwise, read in the packet
712 --------------------------------------------------------------
713*/
714static int smc_rcv()
715{
716 int packet_number;
717 word status;
718 word packet_length;
719 int is_error = 0;
720#ifdef USE_32_BIT
721 dword stat_len;
722#endif
723
724
725 SMC_SELECT_BANK(2);
726 packet_number = SMC_inw( RXFIFO_REG );
727
728 if ( packet_number & RXFIFO_REMPTY ) {
729
730 return 0;
731 }
732
733 PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
734 /* start reading from the start of the packet */
735 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
736
737 /* First two words are status and packet_length */
738#ifdef USE_32_BIT
739 stat_len = SMC_inl(SMC91111_DATA_REG);
740 status = stat_len & 0xffff;
741 packet_length = stat_len >> 16;
742#else
743 status = SMC_inw( SMC91111_DATA_REG );
744 packet_length = SMC_inw( SMC91111_DATA_REG );
745#endif
746
747 packet_length &= 0x07ff; /* mask off top bits */
748
749 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
750
751 if ( !(status & RS_ERRORS ) ){
752 /* Adjust for having already read the first two words */
753 packet_length -= 4; /*4; */
754
755
756
757 /* set odd length for bug in LAN91C111, */
758 /* which never sets RS_ODDFRAME */
759 /* TODO ? */
760
761
762#ifdef USE_32_BIT
763 PRINTK3(" Reading %d dwords (and %d bytes) \n",
764 packet_length >> 2, packet_length & 3 );
765 /* QUESTION: Like in the TX routine, do I want
766 to send the DWORDs or the bytes first, or some
767 mixture. A mixture might improve already slow PIO
768 performance */
769 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
770 /* read the left over bytes */
771 if (packet_length & 3) {
772 int i;
773
wdenk699b13a2002-11-03 18:03:52 +0000774 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
wdenkfe8c2802002-11-03 00:38:21 +0000775 dword leftover = SMC_inl(SMC91111_DATA_REG);
776 for (i=0; i<(packet_length & 3); i++)
777 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
778 }
779#else
780 PRINTK3(" Reading %d words and %d byte(s) \n",
781 (packet_length >> 1 ), packet_length & 1 );
782 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
783
784#endif /* USE_32_BIT */
785
786#if SMC_DEBUG > 2
787 printf("Receiving Packet\n");
788 print_packet( NetRxPackets[0], packet_length );
789#endif
790 } else {
791 /* error ... */
792 /* TODO ? */
793 is_error = 1;
794 }
795
796 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
797 udelay(1); /* Wait until not busy */
798
799 /* error or good, tell the card to get rid of this packet */
800 SMC_outw( MC_RELEASE, MMU_CMD_REG );
801
802 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
803 udelay(1); /* Wait until not busy */
804
805 if (!is_error) {
806 /* Pass the packet up to the protocol layers. */
807 NetReceive(NetRxPackets[0], packet_length);
808 return packet_length;
809 } else {
810 return 0;
811 }
812
813}
814
815
816
817/*----------------------------------------------------
818 . smc_close
819 .
820 . this makes the board clean up everything that it can
821 . and not talk to the outside world. Caused by
822 . an 'ifconfig ethX down'
823 .
824 -----------------------------------------------------*/
825static int smc_close()
826{
827 PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
828
829 /* clear everything */
830 smc_shutdown();
831
832 return 0;
833}
834
835
836#if 0
837/*------------------------------------------------------------
838 . Modify a bit in the LAN91C111 register set
839 .-------------------------------------------------------------*/
840static word smc_modify_regbit(int bank, int ioaddr, int reg,
841 unsigned int bit, int val)
842{
843 word regval;
844
845 SMC_SELECT_BANK( bank );
846
847 regval = SMC_inw( reg );
848 if (val)
849 regval |= bit;
850 else
851 regval &= ~bit;
852
853 SMC_outw( regval, 0 );
854 return(regval);
855}
856
857
858/*------------------------------------------------------------
859 . Retrieve a bit in the LAN91C111 register set
860 .-------------------------------------------------------------*/
861static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
862{
863 SMC_SELECT_BANK( bank );
864 if ( SMC_inw( reg ) & bit)
865 return(1);
866 else
867 return(0);
868}
869
870
871/*------------------------------------------------------------
872 . Modify a LAN91C111 register (word access only)
873 .-------------------------------------------------------------*/
874static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
875{
876 SMC_SELECT_BANK( bank );
877 SMC_outw( val, reg );
878}
879
880
881/*------------------------------------------------------------
882 . Retrieve a LAN91C111 register (word access only)
883 .-------------------------------------------------------------*/
884static int smc_get_reg(int bank, int ioaddr, int reg)
885{
886 SMC_SELECT_BANK( bank );
887 return(SMC_inw( reg ));
888}
889
890#endif /* 0 */
891
892/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
893
894#if (SMC_DEBUG > 2 )
895
896/*------------------------------------------------------------
897 . Debugging function for viewing MII Management serial bitstream
898 .-------------------------------------------------------------*/
899static void smc_dump_mii_stream(byte* bits, int size)
900{
901 int i;
902
903 printf("BIT#:");
904 for (i = 0; i < size; ++i)
905 {
906 printf("%d", i%10);
907 }
908
909 printf("\nMDOE:");
910 for (i = 0; i < size; ++i)
911 {
912 if (bits[i] & MII_MDOE)
913 printf("1");
914 else
915 printf("0");
916 }
917
918 printf("\nMDO :");
919 for (i = 0; i < size; ++i)
920 {
921 if (bits[i] & MII_MDO)
922 printf("1");
923 else
924 printf("0");
925 }
926
927 printf("\nMDI :");
928 for (i = 0; i < size; ++i)
929 {
930 if (bits[i] & MII_MDI)
931 printf("1");
932 else
933 printf("0");
934 }
935
936 printf("\n");
937}
938#endif
939
940/*------------------------------------------------------------
941 . Reads a register from the MII Management serial interface
942 .-------------------------------------------------------------*/
943#ifndef CONFIG_SMC91111_EXT_PHY
944static word smc_read_phy_register(byte phyreg)
945{
946 int oldBank;
947 int i;
948 byte mask;
949 word mii_reg;
950 byte bits[64];
951 int clk_idx = 0;
952 int input_idx;
953 word phydata;
954 byte phyaddr = SMC_PHY_ADDR;
955
956 /* 32 consecutive ones on MDO to establish sync */
957 for (i = 0; i < 32; ++i)
958 bits[clk_idx++] = MII_MDOE | MII_MDO;
959
960 /* Start code <01> */
961 bits[clk_idx++] = MII_MDOE;
962 bits[clk_idx++] = MII_MDOE | MII_MDO;
963
964 /* Read command <10> */
965 bits[clk_idx++] = MII_MDOE | MII_MDO;
966 bits[clk_idx++] = MII_MDOE;
967
968 /* Output the PHY address, msb first */
969 mask = (byte)0x10;
970 for (i = 0; i < 5; ++i)
971 {
972 if (phyaddr & mask)
973 bits[clk_idx++] = MII_MDOE | MII_MDO;
974 else
975 bits[clk_idx++] = MII_MDOE;
976
977 /* Shift to next lowest bit */
978 mask >>= 1;
979 }
980
981 /* Output the phy register number, msb first */
982 mask = (byte)0x10;
983 for (i = 0; i < 5; ++i)
984 {
985 if (phyreg & mask)
986 bits[clk_idx++] = MII_MDOE | MII_MDO;
987 else
988 bits[clk_idx++] = MII_MDOE;
989
990 /* Shift to next lowest bit */
991 mask >>= 1;
992 }
993
994 /* Tristate and turnaround (2 bit times) */
995 bits[clk_idx++] = 0;
996 /*bits[clk_idx++] = 0; */
997
998 /* Input starts at this bit time */
999 input_idx = clk_idx;
1000
1001 /* Will input 16 bits */
1002 for (i = 0; i < 16; ++i)
1003 bits[clk_idx++] = 0;
1004
1005 /* Final clock bit */
1006 bits[clk_idx++] = 0;
1007
1008 /* Save the current bank */
1009 oldBank = SMC_inw( BANK_SELECT );
1010
1011 /* Select bank 3 */
1012 SMC_SELECT_BANK( 3 );
1013
1014 /* Get the current MII register value */
1015 mii_reg = SMC_inw( MII_REG );
1016
1017 /* Turn off all MII Interface bits */
1018 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1019
1020 /* Clock all 64 cycles */
1021 for (i = 0; i < sizeof bits; ++i)
1022 {
1023 /* Clock Low - output data */
1024 SMC_outw( mii_reg | bits[i], MII_REG );
1025 udelay(SMC_PHY_CLOCK_DELAY);
1026
1027
1028 /* Clock Hi - input data */
1029 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1030 udelay(SMC_PHY_CLOCK_DELAY);
1031 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1032 }
1033
1034 /* Return to idle state */
1035 /* Set clock to low, data to low, and output tristated */
1036 SMC_outw( mii_reg, MII_REG );
1037 udelay(SMC_PHY_CLOCK_DELAY);
1038
1039 /* Restore original bank select */
1040 SMC_SELECT_BANK( oldBank );
1041
1042 /* Recover input data */
1043 phydata = 0;
1044 for (i = 0; i < 16; ++i)
1045 {
1046 phydata <<= 1;
1047
1048 if (bits[input_idx++] & MII_MDI)
1049 phydata |= 0x0001;
1050 }
1051
1052#if (SMC_DEBUG > 2 )
1053 printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1054 phyaddr, phyreg, phydata);
1055 smc_dump_mii_stream(bits, sizeof bits);
1056#endif
1057
1058 return(phydata);
1059}
1060
1061
1062/*------------------------------------------------------------
1063 . Writes a register to the MII Management serial interface
1064 .-------------------------------------------------------------*/
1065static void smc_write_phy_register(byte phyreg, word phydata)
1066{
1067 int oldBank;
1068 int i;
1069 word mask;
1070 word mii_reg;
1071 byte bits[65];
1072 int clk_idx = 0;
1073 byte phyaddr = SMC_PHY_ADDR;
1074
1075 /* 32 consecutive ones on MDO to establish sync */
1076 for (i = 0; i < 32; ++i)
1077 bits[clk_idx++] = MII_MDOE | MII_MDO;
1078
1079 /* Start code <01> */
1080 bits[clk_idx++] = MII_MDOE;
1081 bits[clk_idx++] = MII_MDOE | MII_MDO;
1082
1083 /* Write command <01> */
1084 bits[clk_idx++] = MII_MDOE;
1085 bits[clk_idx++] = MII_MDOE | MII_MDO;
1086
1087 /* Output the PHY address, msb first */
1088 mask = (byte)0x10;
1089 for (i = 0; i < 5; ++i)
1090 {
1091 if (phyaddr & mask)
1092 bits[clk_idx++] = MII_MDOE | MII_MDO;
1093 else
1094 bits[clk_idx++] = MII_MDOE;
1095
1096 /* Shift to next lowest bit */
1097 mask >>= 1;
1098 }
1099
1100 /* Output the phy register number, msb first */
1101 mask = (byte)0x10;
1102 for (i = 0; i < 5; ++i)
1103 {
1104 if (phyreg & mask)
1105 bits[clk_idx++] = MII_MDOE | MII_MDO;
1106 else
1107 bits[clk_idx++] = MII_MDOE;
1108
1109 /* Shift to next lowest bit */
1110 mask >>= 1;
1111 }
1112
1113 /* Tristate and turnaround (2 bit times) */
1114 bits[clk_idx++] = 0;
1115 bits[clk_idx++] = 0;
1116
1117 /* Write out 16 bits of data, msb first */
1118 mask = 0x8000;
1119 for (i = 0; i < 16; ++i)
1120 {
1121 if (phydata & mask)
1122 bits[clk_idx++] = MII_MDOE | MII_MDO;
1123 else
1124 bits[clk_idx++] = MII_MDOE;
1125
1126 /* Shift to next lowest bit */
1127 mask >>= 1;
1128 }
1129
1130 /* Final clock bit (tristate) */
1131 bits[clk_idx++] = 0;
1132
1133 /* Save the current bank */
1134 oldBank = SMC_inw( BANK_SELECT );
1135
1136 /* Select bank 3 */
1137 SMC_SELECT_BANK( 3 );
1138
1139 /* Get the current MII register value */
1140 mii_reg = SMC_inw( MII_REG );
1141
1142 /* Turn off all MII Interface bits */
1143 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1144
1145 /* Clock all cycles */
1146 for (i = 0; i < sizeof bits; ++i)
1147 {
1148 /* Clock Low - output data */
1149 SMC_outw( mii_reg | bits[i], MII_REG );
1150 udelay(SMC_PHY_CLOCK_DELAY);
1151
1152
1153 /* Clock Hi - input data */
1154 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1155 udelay(SMC_PHY_CLOCK_DELAY);
1156 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1157 }
1158
1159 /* Return to idle state */
1160 /* Set clock to low, data to low, and output tristated */
1161 SMC_outw( mii_reg, MII_REG );
1162 udelay(SMC_PHY_CLOCK_DELAY);
1163
1164 /* Restore original bank select */
1165 SMC_SELECT_BANK( oldBank );
1166
1167#if (SMC_DEBUG > 2 )
1168 printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1169 phyaddr, phyreg, phydata);
1170 smc_dump_mii_stream(bits, sizeof bits);
1171#endif
1172}
1173#endif /* !CONFIG_SMC91111_EXT_PHY */
1174
1175
1176
1177/*------------------------------------------------------------
1178 . Waits the specified number of milliseconds - kernel friendly
1179 .-------------------------------------------------------------*/
1180#ifndef CONFIG_SMC91111_EXT_PHY
1181static void smc_wait_ms(unsigned int ms)
1182{
1183 udelay(ms*1000);
1184}
1185#endif /* !CONFIG_SMC91111_EXT_PHY */
1186
1187
1188
1189/*------------------------------------------------------------
1190 . Configures the specified PHY using Autonegotiation. Calls
1191 . smc_phy_fixed() if the user has requested a certain config.
1192 .-------------------------------------------------------------*/
1193#ifndef CONFIG_SMC91111_EXT_PHY
1194static void smc_phy_configure()
1195{
1196 int timeout;
1197 byte phyaddr;
1198 word my_phy_caps; /* My PHY capabilities */
1199 word my_ad_caps; /* My Advertised capabilities */
1200 word status = 0; /*;my status = 0 */
1201 int failed = 0;
1202
1203 PRINTK3("%s:smc_program_phy()\n", SMC_DEV_NAME);
1204
1205
1206
1207 /* Get the detected phy address */
1208 phyaddr = SMC_PHY_ADDR;
1209
1210 /* Reset the PHY, setting all other bits to zero */
1211 smc_write_phy_register(PHY_CNTL_REG, PHY_CNTL_RST);
1212
1213 /* Wait for the reset to complete, or time out */
1214 timeout = 6; /* Wait up to 3 seconds */
1215 while (timeout--)
1216 {
1217 if (!(smc_read_phy_register(PHY_CNTL_REG)
1218 & PHY_CNTL_RST))
1219 {
1220 /* reset complete */
1221 break;
1222 }
1223
1224 smc_wait_ms(500); /* wait 500 millisecs */
1225 }
1226
1227 if (timeout < 1)
1228 {
1229 printf("%s:PHY reset timed out\n", SMC_DEV_NAME);
1230 goto smc_phy_configure_exit;
1231 }
1232
1233 /* Read PHY Register 18, Status Output */
1234 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1235
1236 /* Enable PHY Interrupts (for register 18) */
1237 /* Interrupts listed here are disabled */
1238 smc_write_phy_register(PHY_INT_REG, 0xffff);
1239
1240 /* Configure the Receive/Phy Control register */
1241 SMC_SELECT_BANK( 0 );
1242 SMC_outw( RPC_DEFAULT, RPC_REG );
1243
1244 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1245 my_phy_caps = smc_read_phy_register(PHY_STAT_REG);
1246 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1247
1248 if (my_phy_caps & PHY_STAT_CAP_T4)
1249 my_ad_caps |= PHY_AD_T4;
1250
1251 if (my_phy_caps & PHY_STAT_CAP_TXF)
1252 my_ad_caps |= PHY_AD_TX_FDX;
1253
1254 if (my_phy_caps & PHY_STAT_CAP_TXH)
1255 my_ad_caps |= PHY_AD_TX_HDX;
1256
1257 if (my_phy_caps & PHY_STAT_CAP_TF)
1258 my_ad_caps |= PHY_AD_10_FDX;
1259
1260 if (my_phy_caps & PHY_STAT_CAP_TH)
1261 my_ad_caps |= PHY_AD_10_HDX;
1262
1263 /* Update our Auto-Neg Advertisement Register */
1264 smc_write_phy_register( PHY_AD_REG, my_ad_caps);
1265
1266 PRINTK2("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1267 PRINTK2("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1268
1269 /* Restart auto-negotiation process in order to advertise my caps */
1270 smc_write_phy_register( PHY_CNTL_REG,
1271 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
1272
1273 /* Wait for the auto-negotiation to complete. This may take from */
1274 /* 2 to 3 seconds. */
1275 /* Wait for the reset to complete, or time out */
1276 timeout = 20; /* Wait up to 10 seconds */
1277 while (timeout--)
1278 {
1279 status = smc_read_phy_register( PHY_STAT_REG);
1280 if (status & PHY_STAT_ANEG_ACK)
1281 {
1282 /* auto-negotiate complete */
1283 break;
1284 }
1285
1286 smc_wait_ms(500); /* wait 500 millisecs */
1287
1288 /* Restart auto-negotiation if remote fault */
1289 if (status & PHY_STAT_REM_FLT)
1290 {
1291 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1292
1293 /* Restart auto-negotiation */
1294 printf("%s:PHY restarting auto-negotiation\n",
1295 SMC_DEV_NAME);
1296 smc_write_phy_register( PHY_CNTL_REG,
1297 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
1298 PHY_CNTL_SPEED | PHY_CNTL_DPLX);
1299 }
1300 }
1301
1302 if (timeout < 1)
1303 {
1304 printf("%s:PHY auto-negotiate timed out\n",
1305 SMC_DEV_NAME);
1306 printf("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1307 failed = 1;
1308 }
1309
1310 /* Fail if we detected an auto-negotiate remote fault */
1311 if (status & PHY_STAT_REM_FLT)
1312 {
1313 printf( "%s:PHY remote fault detected\n", SMC_DEV_NAME);
1314 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1315 failed = 1;
1316 }
1317
1318 /* Re-Configure the Receive/Phy Control register */
1319 SMC_outw( RPC_DEFAULT, RPC_REG );
1320
1321 smc_phy_configure_exit:
1322
1323}
1324#endif /* !CONFIG_SMC91111_EXT_PHY */
1325
1326
1327#if SMC_DEBUG > 2
1328static void print_packet( byte * buf, int length )
1329{
1330#if 0
1331 int i;
1332 int remainder;
1333 int lines;
1334
1335 printf("Packet of length %d \n", length );
1336
1337#if SMC_DEBUG > 3
1338 lines = length / 16;
1339 remainder = length % 16;
1340
1341 for ( i = 0; i < lines ; i ++ ) {
1342 int cur;
1343
1344 for ( cur = 0; cur < 8; cur ++ ) {
1345 byte a, b;
1346
1347 a = *(buf ++ );
1348 b = *(buf ++ );
1349 printf("%02x%02x ", a, b );
1350 }
1351 printf("\n");
1352 }
1353 for ( i = 0; i < remainder/2 ; i++ ) {
1354 byte a, b;
1355
1356 a = *(buf ++ );
1357 b = *(buf ++ );
1358 printf("%02x%02x ", a, b );
1359 }
1360 printf("\n");
1361#endif
1362#endif
1363}
1364#endif
1365
1366int eth_init(bd_t *bd) {
1367 smc_open();
1368 return 0;
1369}
1370
1371void eth_halt() {
1372 smc_close();
1373}
1374
1375int eth_rx() {
1376 return smc_rcv();
1377}
1378
1379int eth_send(volatile void *packet, int length) {
1380 return smc_send_packet(packet, length);
1381}
1382
1383#endif /* CONFIG_DRIVER_SMC91111 */