blob: 00b2fed7b74aef30ec3352ad9699847d88151e7d [file] [log] [blame]
Simon Glass18530302013-03-19 04:58:56 +00001/*
2 * Copyright (c) 2011-12 The Chromium OS Authors.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Simon Glass18530302013-03-19 04:58:56 +00005 *
6 * This file is derived from the flashrom project.
7 */
Bin Meng9eb43392016-02-01 01:40:36 -08008
Simon Glass18530302013-03-19 04:58:56 +00009#include <common.h>
Simon Glassba457562015-03-26 09:29:26 -060010#include <dm.h>
Simon Glass5093bad2015-01-27 22:13:43 -070011#include <errno.h>
Simon Glass18530302013-03-19 04:58:56 +000012#include <malloc.h>
Simon Glassf2b85ab2016-01-18 20:19:21 -070013#include <pch.h>
Simon Glass18530302013-03-19 04:58:56 +000014#include <pci.h>
15#include <pci_ids.h>
Simon Glassf2b85ab2016-01-18 20:19:21 -070016#include <spi.h>
Simon Glass18530302013-03-19 04:58:56 +000017#include <asm/io.h>
18
19#include "ich.h"
20
Bin Meng1f9eb592016-02-01 01:40:37 -080021DECLARE_GLOBAL_DATA_PTR;
22
Simon Glassfffe25d2016-01-18 20:19:20 -070023#ifdef DEBUG_TRACE
24#define debug_trace(fmt, args...) debug(fmt, ##args)
25#else
26#define debug_trace(x, args...)
27#endif
28
Simon Glassba457562015-03-26 09:29:26 -060029static u8 ich_readb(struct ich_spi_priv *priv, int reg)
Simon Glass18530302013-03-19 04:58:56 +000030{
Simon Glassba457562015-03-26 09:29:26 -060031 u8 value = readb(priv->base + reg);
Simon Glass18530302013-03-19 04:58:56 +000032
Simon Glassfffe25d2016-01-18 20:19:20 -070033 debug_trace("read %2.2x from %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000034
35 return value;
36}
37
Simon Glassba457562015-03-26 09:29:26 -060038static u16 ich_readw(struct ich_spi_priv *priv, int reg)
Simon Glass18530302013-03-19 04:58:56 +000039{
Simon Glassba457562015-03-26 09:29:26 -060040 u16 value = readw(priv->base + reg);
Simon Glass18530302013-03-19 04:58:56 +000041
Simon Glassfffe25d2016-01-18 20:19:20 -070042 debug_trace("read %4.4x from %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000043
44 return value;
45}
46
Simon Glassba457562015-03-26 09:29:26 -060047static u32 ich_readl(struct ich_spi_priv *priv, int reg)
Simon Glass18530302013-03-19 04:58:56 +000048{
Simon Glassba457562015-03-26 09:29:26 -060049 u32 value = readl(priv->base + reg);
Simon Glass18530302013-03-19 04:58:56 +000050
Simon Glassfffe25d2016-01-18 20:19:20 -070051 debug_trace("read %8.8x from %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000052
53 return value;
54}
55
Simon Glassba457562015-03-26 09:29:26 -060056static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
Simon Glass18530302013-03-19 04:58:56 +000057{
Simon Glassba457562015-03-26 09:29:26 -060058 writeb(value, priv->base + reg);
Simon Glassfffe25d2016-01-18 20:19:20 -070059 debug_trace("wrote %2.2x to %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000060}
61
Simon Glassba457562015-03-26 09:29:26 -060062static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
Simon Glass18530302013-03-19 04:58:56 +000063{
Simon Glassba457562015-03-26 09:29:26 -060064 writew(value, priv->base + reg);
Simon Glassfffe25d2016-01-18 20:19:20 -070065 debug_trace("wrote %4.4x to %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000066}
67
Simon Glassba457562015-03-26 09:29:26 -060068static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
Simon Glass18530302013-03-19 04:58:56 +000069{
Simon Glassba457562015-03-26 09:29:26 -060070 writel(value, priv->base + reg);
Simon Glassfffe25d2016-01-18 20:19:20 -070071 debug_trace("wrote %8.8x to %4.4x\n", value, reg);
Simon Glass18530302013-03-19 04:58:56 +000072}
73
Simon Glassba457562015-03-26 09:29:26 -060074static void write_reg(struct ich_spi_priv *priv, const void *value,
75 int dest_reg, uint32_t size)
Simon Glass18530302013-03-19 04:58:56 +000076{
Simon Glassba457562015-03-26 09:29:26 -060077 memcpy_toio(priv->base + dest_reg, value, size);
Simon Glass18530302013-03-19 04:58:56 +000078}
79
Simon Glassba457562015-03-26 09:29:26 -060080static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
81 uint32_t size)
Simon Glass18530302013-03-19 04:58:56 +000082{
Simon Glassba457562015-03-26 09:29:26 -060083 memcpy_fromio(value, priv->base + src_reg, size);
Simon Glass18530302013-03-19 04:58:56 +000084}
85
Simon Glassba457562015-03-26 09:29:26 -060086static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
Simon Glass18530302013-03-19 04:58:56 +000087{
88 const uint32_t bbar_mask = 0x00ffff00;
89 uint32_t ichspi_bbar;
90
91 minaddr &= bbar_mask;
Simon Glassba457562015-03-26 09:29:26 -060092 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
Simon Glass18530302013-03-19 04:58:56 +000093 ichspi_bbar |= minaddr;
Simon Glassba457562015-03-26 09:29:26 -060094 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
Simon Glass18530302013-03-19 04:58:56 +000095}
96
Simon Glass18530302013-03-19 04:58:56 +000097/* @return 1 if the SPI flash supports the 33MHz speed */
Simon Glassf2b85ab2016-01-18 20:19:21 -070098static int ich9_can_do_33mhz(struct udevice *dev)
Simon Glass18530302013-03-19 04:58:56 +000099{
100 u32 fdod, speed;
101
102 /* Observe SPI Descriptor Component Section 0 */
Simon Glassf2b85ab2016-01-18 20:19:21 -0700103 dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
Simon Glass18530302013-03-19 04:58:56 +0000104
105 /* Extract the Write/Erase SPI Frequency from descriptor */
Simon Glassf2b85ab2016-01-18 20:19:21 -0700106 dm_pci_read_config32(dev->parent, 0xb4, &fdod);
Simon Glass18530302013-03-19 04:58:56 +0000107
108 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
109 speed = (fdod >> 21) & 7;
110
111 return speed == 1;
112}
113
Simon Glassf2b85ab2016-01-18 20:19:21 -0700114static int ich_init_controller(struct udevice *dev,
115 struct ich_spi_platdata *plat,
Simon Glassba457562015-03-26 09:29:26 -0600116 struct ich_spi_priv *ctlr)
Simon Glass18530302013-03-19 04:58:56 +0000117{
Simon Glassf2b85ab2016-01-18 20:19:21 -0700118 ulong sbase_addr;
119 void *sbase;
Simon Glass5093bad2015-01-27 22:13:43 -0700120
121 /* SBASE is similar */
Bin Meng3e389d82016-02-01 01:40:42 -0800122 pch_get_spi_base(dev->parent, &sbase_addr);
Simon Glassf2b85ab2016-01-18 20:19:21 -0700123 sbase = (void *)sbase_addr;
124 debug("%s: sbase=%p\n", __func__, sbase);
Simon Glass5093bad2015-01-27 22:13:43 -0700125
Bin Meng6e670b52016-02-01 01:40:38 -0800126 if (plat->ich_version == ICHV_7) {
Simon Glassf2b85ab2016-01-18 20:19:21 -0700127 struct ich7_spi_regs *ich7_spi = sbase;
Simon Glass18530302013-03-19 04:58:56 +0000128
Simon Glassf2b85ab2016-01-18 20:19:21 -0700129 ich7_spi = (struct ich7_spi_regs *)sbase;
Simon Glassba457562015-03-26 09:29:26 -0600130 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
131 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
Simon Glass18530302013-03-19 04:58:56 +0000132 ctlr->menubytes = sizeof(ich7_spi->opmenu);
Simon Glassba457562015-03-26 09:29:26 -0600133 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
134 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
135 ctlr->data = offsetof(struct ich7_spi_regs, spid);
Simon Glass18530302013-03-19 04:58:56 +0000136 ctlr->databytes = sizeof(ich7_spi->spid);
Simon Glassba457562015-03-26 09:29:26 -0600137 ctlr->status = offsetof(struct ich7_spi_regs, spis);
138 ctlr->control = offsetof(struct ich7_spi_regs, spic);
139 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
140 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
Simon Glass18530302013-03-19 04:58:56 +0000141 ctlr->base = ich7_spi;
Bin Meng6e670b52016-02-01 01:40:38 -0800142 } else if (plat->ich_version == ICHV_9) {
Simon Glassf2b85ab2016-01-18 20:19:21 -0700143 struct ich9_spi_regs *ich9_spi = sbase;
Simon Glass18530302013-03-19 04:58:56 +0000144
Simon Glassba457562015-03-26 09:29:26 -0600145 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
146 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
Simon Glass18530302013-03-19 04:58:56 +0000147 ctlr->menubytes = sizeof(ich9_spi->opmenu);
Simon Glassba457562015-03-26 09:29:26 -0600148 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
149 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
150 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
Simon Glass18530302013-03-19 04:58:56 +0000151 ctlr->databytes = sizeof(ich9_spi->fdata);
Simon Glassba457562015-03-26 09:29:26 -0600152 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
153 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
154 ctlr->speed = ctlr->control + 2;
155 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
156 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
Simon Glass50787922015-07-03 18:28:22 -0600157 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
Simon Glass18530302013-03-19 04:58:56 +0000158 ctlr->pr = &ich9_spi->pr[0];
159 ctlr->base = ich9_spi;
160 } else {
Simon Glassba457562015-03-26 09:29:26 -0600161 debug("ICH SPI: Unrecognised ICH version %d\n",
162 plat->ich_version);
163 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000164 }
Simon Glass18530302013-03-19 04:58:56 +0000165
166 /* Work out the maximum speed we can support */
167 ctlr->max_speed = 20000000;
Bin Meng6e670b52016-02-01 01:40:38 -0800168 if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
Simon Glass18530302013-03-19 04:58:56 +0000169 ctlr->max_speed = 33000000;
Simon Glassf2b85ab2016-01-18 20:19:21 -0700170 debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
Simon Glassba457562015-03-26 09:29:26 -0600171 plat->ich_version, ctlr->base, ctlr->max_speed);
Simon Glass18530302013-03-19 04:58:56 +0000172
173 ich_set_bbar(ctlr, 0);
174
175 return 0;
176}
177
Simon Glass18530302013-03-19 04:58:56 +0000178static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
179{
180 trans->out += bytes;
181 trans->bytesout -= bytes;
182}
183
184static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
185{
186 trans->in += bytes;
187 trans->bytesin -= bytes;
188}
189
190static void spi_setup_type(struct spi_trans *trans, int data_bytes)
191{
192 trans->type = 0xFF;
193
Bin Meng9eb43392016-02-01 01:40:36 -0800194 /* Try to guess spi type from read/write sizes */
Simon Glass18530302013-03-19 04:58:56 +0000195 if (trans->bytesin == 0) {
196 if (trans->bytesout + data_bytes > 4)
197 /*
198 * If bytesin = 0 and bytesout > 4, we presume this is
199 * a write data operation, which is accompanied by an
200 * address.
201 */
202 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
203 else
204 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
205 return;
206 }
207
208 if (trans->bytesout == 1) { /* and bytesin is > 0 */
209 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
210 return;
211 }
212
213 if (trans->bytesout == 4) /* and bytesin is > 0 */
214 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
215
216 /* Fast read command is called with 5 bytes instead of 4 */
217 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
218 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
219 --trans->bytesout;
220 }
221}
222
Simon Glassba457562015-03-26 09:29:26 -0600223static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
Simon Glass18530302013-03-19 04:58:56 +0000224{
225 uint16_t optypes;
Simon Glassba457562015-03-26 09:29:26 -0600226 uint8_t opmenu[ctlr->menubytes];
Simon Glass18530302013-03-19 04:58:56 +0000227
228 trans->opcode = trans->out[0];
229 spi_use_out(trans, 1);
Simon Glassba457562015-03-26 09:29:26 -0600230 if (!ctlr->ichspi_lock) {
Simon Glass18530302013-03-19 04:58:56 +0000231 /* The lock is off, so just use index 0. */
Simon Glassba457562015-03-26 09:29:26 -0600232 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
233 optypes = ich_readw(ctlr, ctlr->optype);
Simon Glass18530302013-03-19 04:58:56 +0000234 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
Simon Glassba457562015-03-26 09:29:26 -0600235 ich_writew(ctlr, optypes, ctlr->optype);
Simon Glass18530302013-03-19 04:58:56 +0000236 return 0;
237 } else {
238 /* The lock is on. See if what we need is on the menu. */
239 uint8_t optype;
240 uint16_t opcode_index;
241
242 /* Write Enable is handled as atomic prefix */
243 if (trans->opcode == SPI_OPCODE_WREN)
244 return 0;
245
Simon Glassba457562015-03-26 09:29:26 -0600246 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
247 for (opcode_index = 0; opcode_index < ctlr->menubytes;
Simon Glass18530302013-03-19 04:58:56 +0000248 opcode_index++) {
249 if (opmenu[opcode_index] == trans->opcode)
250 break;
251 }
252
Simon Glassba457562015-03-26 09:29:26 -0600253 if (opcode_index == ctlr->menubytes) {
Simon Glass18530302013-03-19 04:58:56 +0000254 printf("ICH SPI: Opcode %x not found\n",
255 trans->opcode);
Simon Glassba457562015-03-26 09:29:26 -0600256 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000257 }
258
Simon Glassba457562015-03-26 09:29:26 -0600259 optypes = ich_readw(ctlr, ctlr->optype);
Simon Glass18530302013-03-19 04:58:56 +0000260 optype = (optypes >> (opcode_index * 2)) & 0x3;
261 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
262 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
263 trans->bytesout >= 3) {
264 /* We guessed wrong earlier. Fix it up. */
265 trans->type = optype;
266 }
267 if (optype != trans->type) {
268 printf("ICH SPI: Transaction doesn't fit type %d\n",
269 optype);
Simon Glassba457562015-03-26 09:29:26 -0600270 return -ENOSPC;
Simon Glass18530302013-03-19 04:58:56 +0000271 }
272 return opcode_index;
273 }
274}
275
276static int spi_setup_offset(struct spi_trans *trans)
277{
Bin Meng9eb43392016-02-01 01:40:36 -0800278 /* Separate the SPI address and data */
Simon Glass18530302013-03-19 04:58:56 +0000279 switch (trans->type) {
280 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
281 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
282 return 0;
283 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
284 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
285 trans->offset = ((uint32_t)trans->out[0] << 16) |
286 ((uint32_t)trans->out[1] << 8) |
287 ((uint32_t)trans->out[2] << 0);
288 spi_use_out(trans, 3);
289 return 1;
290 default:
291 printf("Unrecognized SPI transaction type %#x\n", trans->type);
Simon Glassba457562015-03-26 09:29:26 -0600292 return -EPROTO;
Simon Glass18530302013-03-19 04:58:56 +0000293 }
294}
295
296/*
297 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
York Sun472d5462013-04-01 11:29:11 -0700298 * below is true) or 0. In case the wait was for the bit(s) to set - write
Simon Glass18530302013-03-19 04:58:56 +0000299 * those bits back, which would cause resetting them.
300 *
301 * Return the last read status value on success or -1 on failure.
302 */
Simon Glassba457562015-03-26 09:29:26 -0600303static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
304 int wait_til_set)
Simon Glass18530302013-03-19 04:58:56 +0000305{
306 int timeout = 600000; /* This will result in 6s */
307 u16 status = 0;
308
309 while (timeout--) {
Simon Glassba457562015-03-26 09:29:26 -0600310 status = ich_readw(ctlr, ctlr->status);
Simon Glass18530302013-03-19 04:58:56 +0000311 if (wait_til_set ^ ((status & bitmask) == 0)) {
Simon Glassba457562015-03-26 09:29:26 -0600312 if (wait_til_set) {
313 ich_writew(ctlr, status & bitmask,
314 ctlr->status);
315 }
Simon Glass18530302013-03-19 04:58:56 +0000316 return status;
317 }
318 udelay(10);
319 }
320
321 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
322 status, bitmask);
Simon Glassba457562015-03-26 09:29:26 -0600323 return -ETIMEDOUT;
Simon Glass18530302013-03-19 04:58:56 +0000324}
325
Simon Glassba457562015-03-26 09:29:26 -0600326static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
327 const void *dout, void *din, unsigned long flags)
Simon Glass18530302013-03-19 04:58:56 +0000328{
Simon Glassba457562015-03-26 09:29:26 -0600329 struct udevice *bus = dev_get_parent(dev);
Simon Glasse1e332c2015-07-03 18:28:21 -0600330 struct ich_spi_platdata *plat = dev_get_platdata(bus);
Simon Glassba457562015-03-26 09:29:26 -0600331 struct ich_spi_priv *ctlr = dev_get_priv(bus);
Simon Glass18530302013-03-19 04:58:56 +0000332 uint16_t control;
333 int16_t opcode_index;
334 int with_address;
335 int status;
336 int bytes = bitlen / 8;
Simon Glassba457562015-03-26 09:29:26 -0600337 struct spi_trans *trans = &ctlr->trans;
Simon Glass18530302013-03-19 04:58:56 +0000338 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
339 int using_cmd = 0;
Simon Glassba457562015-03-26 09:29:26 -0600340 int ret;
Simon Glass18530302013-03-19 04:58:56 +0000341
Simon Glass5d4a7572015-06-07 08:50:33 -0600342 /* We don't support writing partial bytes */
Simon Glass18530302013-03-19 04:58:56 +0000343 if (bitlen % 8) {
344 debug("ICH SPI: Accessing partial bytes not supported\n");
Simon Glassba457562015-03-26 09:29:26 -0600345 return -EPROTONOSUPPORT;
Simon Glass18530302013-03-19 04:58:56 +0000346 }
347
348 /* An empty end transaction can be ignored */
349 if (type == SPI_XFER_END && !dout && !din)
350 return 0;
351
352 if (type & SPI_XFER_BEGIN)
353 memset(trans, '\0', sizeof(*trans));
354
355 /* Dp we need to come back later to finish it? */
356 if (dout && type == SPI_XFER_BEGIN) {
357 if (bytes > ICH_MAX_CMD_LEN) {
358 debug("ICH SPI: Command length limit exceeded\n");
Simon Glassba457562015-03-26 09:29:26 -0600359 return -ENOSPC;
Simon Glass18530302013-03-19 04:58:56 +0000360 }
361 memcpy(trans->cmd, dout, bytes);
362 trans->cmd_len = bytes;
Simon Glassfffe25d2016-01-18 20:19:20 -0700363 debug_trace("ICH SPI: Saved %d bytes\n", bytes);
Simon Glass18530302013-03-19 04:58:56 +0000364 return 0;
365 }
366
367 /*
368 * We process a 'middle' spi_xfer() call, which has no
369 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
370 * an end. We therefore repeat the command. This is because ICH
371 * seems to have no support for this, or because interest (in digging
372 * out the details and creating a special case in the code) is low.
373 */
374 if (trans->cmd_len) {
375 trans->out = trans->cmd;
376 trans->bytesout = trans->cmd_len;
377 using_cmd = 1;
Simon Glassfffe25d2016-01-18 20:19:20 -0700378 debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
Simon Glass18530302013-03-19 04:58:56 +0000379 } else {
380 trans->out = dout;
381 trans->bytesout = dout ? bytes : 0;
382 }
383
384 trans->in = din;
385 trans->bytesin = din ? bytes : 0;
386
Bin Meng9eb43392016-02-01 01:40:36 -0800387 /* There has to always at least be an opcode */
Simon Glass18530302013-03-19 04:58:56 +0000388 if (!trans->bytesout) {
389 debug("ICH SPI: No opcode for transfer\n");
Simon Glassba457562015-03-26 09:29:26 -0600390 return -EPROTO;
Simon Glass18530302013-03-19 04:58:56 +0000391 }
392
Simon Glassba457562015-03-26 09:29:26 -0600393 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
394 if (ret < 0)
395 return ret;
Simon Glass18530302013-03-19 04:58:56 +0000396
Bin Meng6e670b52016-02-01 01:40:38 -0800397 if (plat->ich_version == ICHV_7)
Simon Glasse1e332c2015-07-03 18:28:21 -0600398 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
399 else
400 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
Simon Glass18530302013-03-19 04:58:56 +0000401
402 spi_setup_type(trans, using_cmd ? bytes : 0);
Simon Glassba457562015-03-26 09:29:26 -0600403 opcode_index = spi_setup_opcode(ctlr, trans);
Simon Glass18530302013-03-19 04:58:56 +0000404 if (opcode_index < 0)
Simon Glassba457562015-03-26 09:29:26 -0600405 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000406 with_address = spi_setup_offset(trans);
407 if (with_address < 0)
Simon Glassba457562015-03-26 09:29:26 -0600408 return -EINVAL;
Simon Glass18530302013-03-19 04:58:56 +0000409
410 if (trans->opcode == SPI_OPCODE_WREN) {
411 /*
412 * Treat Write Enable as Atomic Pre-Op if possible
413 * in order to prevent the Management Engine from
414 * issuing a transaction between WREN and DATA.
415 */
Simon Glassba457562015-03-26 09:29:26 -0600416 if (!ctlr->ichspi_lock)
417 ich_writew(ctlr, trans->opcode, ctlr->preop);
Simon Glass18530302013-03-19 04:58:56 +0000418 return 0;
419 }
420
Simon Glassba457562015-03-26 09:29:26 -0600421 if (ctlr->speed && ctlr->max_speed >= 33000000) {
Simon Glass18530302013-03-19 04:58:56 +0000422 int byte;
423
Simon Glassba457562015-03-26 09:29:26 -0600424 byte = ich_readb(ctlr, ctlr->speed);
425 if (ctlr->cur_speed >= 33000000)
Simon Glass18530302013-03-19 04:58:56 +0000426 byte |= SSFC_SCF_33MHZ;
427 else
428 byte &= ~SSFC_SCF_33MHZ;
Simon Glassba457562015-03-26 09:29:26 -0600429 ich_writeb(ctlr, byte, ctlr->speed);
Simon Glass18530302013-03-19 04:58:56 +0000430 }
431
432 /* See if we have used up the command data */
433 if (using_cmd && dout && bytes) {
434 trans->out = dout;
435 trans->bytesout = bytes;
Simon Glassfffe25d2016-01-18 20:19:20 -0700436 debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
Simon Glass18530302013-03-19 04:58:56 +0000437 }
438
439 /* Preset control fields */
Simon Glassba457562015-03-26 09:29:26 -0600440 control = ich_readw(ctlr, ctlr->control);
Simon Glass18530302013-03-19 04:58:56 +0000441 control &= ~SSFC_RESERVED;
442 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
443
444 /* Issue atomic preop cycle if needed */
Simon Glassba457562015-03-26 09:29:26 -0600445 if (ich_readw(ctlr, ctlr->preop))
Simon Glass18530302013-03-19 04:58:56 +0000446 control |= SPIC_ACS;
447
448 if (!trans->bytesout && !trans->bytesin) {
449 /* SPI addresses are 24 bit only */
Simon Glassba457562015-03-26 09:29:26 -0600450 if (with_address) {
451 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
452 ctlr->addr);
453 }
Simon Glass18530302013-03-19 04:58:56 +0000454 /*
455 * This is a 'no data' command (like Write Enable), its
456 * bitesout size was 1, decremented to zero while executing
457 * spi_setup_opcode() above. Tell the chip to send the
458 * command.
459 */
Simon Glassba457562015-03-26 09:29:26 -0600460 ich_writew(ctlr, control, ctlr->control);
Simon Glass18530302013-03-19 04:58:56 +0000461
462 /* wait for the result */
Simon Glassba457562015-03-26 09:29:26 -0600463 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
464 if (status < 0)
465 return status;
Simon Glass18530302013-03-19 04:58:56 +0000466
467 if (status & SPIS_FCERR) {
468 debug("ICH SPI: Command transaction error\n");
Simon Glassba457562015-03-26 09:29:26 -0600469 return -EIO;
Simon Glass18530302013-03-19 04:58:56 +0000470 }
471
472 return 0;
473 }
474
475 /*
476 * Check if this is a write command atempting to transfer more bytes
477 * than the controller can handle. Iterations for writes are not
478 * supported here because each SPI write command needs to be preceded
479 * and followed by other SPI commands, and this sequence is controlled
480 * by the SPI chip driver.
481 */
Simon Glassba457562015-03-26 09:29:26 -0600482 if (trans->bytesout > ctlr->databytes) {
Simon Glass18530302013-03-19 04:58:56 +0000483 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
Simon Glassba457562015-03-26 09:29:26 -0600484 return -EPROTO;
Simon Glass18530302013-03-19 04:58:56 +0000485 }
486
487 /*
488 * Read or write up to databytes bytes at a time until everything has
489 * been sent.
490 */
491 while (trans->bytesout || trans->bytesin) {
492 uint32_t data_length;
Simon Glass18530302013-03-19 04:58:56 +0000493
494 /* SPI addresses are 24 bit only */
Simon Glassba457562015-03-26 09:29:26 -0600495 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
Simon Glass18530302013-03-19 04:58:56 +0000496
497 if (trans->bytesout)
Simon Glassba457562015-03-26 09:29:26 -0600498 data_length = min(trans->bytesout, ctlr->databytes);
Simon Glass18530302013-03-19 04:58:56 +0000499 else
Simon Glassba457562015-03-26 09:29:26 -0600500 data_length = min(trans->bytesin, ctlr->databytes);
Simon Glass18530302013-03-19 04:58:56 +0000501
502 /* Program data into FDATA0 to N */
503 if (trans->bytesout) {
Simon Glassba457562015-03-26 09:29:26 -0600504 write_reg(ctlr, trans->out, ctlr->data, data_length);
Simon Glass18530302013-03-19 04:58:56 +0000505 spi_use_out(trans, data_length);
506 if (with_address)
507 trans->offset += data_length;
508 }
509
510 /* Add proper control fields' values */
Simon Glassba457562015-03-26 09:29:26 -0600511 control &= ~((ctlr->databytes - 1) << 8);
Simon Glass18530302013-03-19 04:58:56 +0000512 control |= SPIC_DS;
513 control |= (data_length - 1) << 8;
514
515 /* write it */
Simon Glassba457562015-03-26 09:29:26 -0600516 ich_writew(ctlr, control, ctlr->control);
Simon Glass18530302013-03-19 04:58:56 +0000517
Bin Meng9eb43392016-02-01 01:40:36 -0800518 /* Wait for Cycle Done Status or Flash Cycle Error */
Simon Glassba457562015-03-26 09:29:26 -0600519 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
520 if (status < 0)
521 return status;
Simon Glass18530302013-03-19 04:58:56 +0000522
523 if (status & SPIS_FCERR) {
Simon Glass5d4a7572015-06-07 08:50:33 -0600524 debug("ICH SPI: Data transaction error %x\n", status);
Simon Glassba457562015-03-26 09:29:26 -0600525 return -EIO;
Simon Glass18530302013-03-19 04:58:56 +0000526 }
527
528 if (trans->bytesin) {
Simon Glassba457562015-03-26 09:29:26 -0600529 read_reg(ctlr, ctlr->data, trans->in, data_length);
Simon Glass18530302013-03-19 04:58:56 +0000530 spi_use_in(trans, data_length);
531 if (with_address)
532 trans->offset += data_length;
533 }
534 }
535
536 /* Clear atomic preop now that xfer is done */
Simon Glassba457562015-03-26 09:29:26 -0600537 ich_writew(ctlr, 0, ctlr->preop);
Simon Glass18530302013-03-19 04:58:56 +0000538
539 return 0;
540}
541
Simon Glass18530302013-03-19 04:58:56 +0000542/*
543 * This uses the SPI controller from the Intel Cougar Point and Panther Point
544 * PCH to write-protect portions of the SPI flash until reboot. The changes
545 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
546 * done elsewhere.
547 */
Simon Glassba457562015-03-26 09:29:26 -0600548int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
549 uint32_t length, int hint)
Simon Glass18530302013-03-19 04:58:56 +0000550{
Simon Glassba457562015-03-26 09:29:26 -0600551 struct udevice *bus = dev->parent;
552 struct ich_spi_priv *ctlr = dev_get_priv(bus);
Simon Glass18530302013-03-19 04:58:56 +0000553 uint32_t tmplong;
554 uint32_t upper_limit;
555
Simon Glassba457562015-03-26 09:29:26 -0600556 if (!ctlr->pr) {
Simon Glass18530302013-03-19 04:58:56 +0000557 printf("%s: operation not supported on this chipset\n",
558 __func__);
Simon Glassba457562015-03-26 09:29:26 -0600559 return -ENOSYS;
Simon Glass18530302013-03-19 04:58:56 +0000560 }
561
562 if (length == 0 ||
563 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
564 hint < 0 || hint > 4) {
565 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
566 lower_limit, length, hint);
Simon Glassba457562015-03-26 09:29:26 -0600567 return -EPERM;
Simon Glass18530302013-03-19 04:58:56 +0000568 }
569
570 upper_limit = lower_limit + length - 1;
571
572 /*
573 * Determine bits to write, as follows:
574 * 31 Write-protection enable (includes erase operation)
575 * 30:29 reserved
576 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
577 * 15 Read-protection enable
578 * 14:13 reserved
579 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
580 */
581 tmplong = 0x80000000 |
582 ((upper_limit & 0x01fff000) << 4) |
583 ((lower_limit & 0x01fff000) >> 12);
584
585 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
Simon Glassba457562015-03-26 09:29:26 -0600586 &ctlr->pr[hint]);
587 ctlr->pr[hint] = tmplong;
Simon Glass18530302013-03-19 04:58:56 +0000588
589 return 0;
590}
Simon Glassba457562015-03-26 09:29:26 -0600591
Simon Glassf2b85ab2016-01-18 20:19:21 -0700592static int ich_spi_probe(struct udevice *dev)
Simon Glassba457562015-03-26 09:29:26 -0600593{
Simon Glassf2b85ab2016-01-18 20:19:21 -0700594 struct ich_spi_platdata *plat = dev_get_platdata(dev);
595 struct ich_spi_priv *priv = dev_get_priv(dev);
Simon Glassba457562015-03-26 09:29:26 -0600596 uint8_t bios_cntl;
597 int ret;
598
Simon Glassf2b85ab2016-01-18 20:19:21 -0700599 ret = ich_init_controller(dev, plat, priv);
Simon Glassba457562015-03-26 09:29:26 -0600600 if (ret)
601 return ret;
Simon Glassf2b85ab2016-01-18 20:19:21 -0700602 /* Disable the BIOS write protect so write commands are allowed */
603 ret = pch_set_spi_protect(dev->parent, false);
604 if (ret == -ENOSYS) {
Simon Glass50787922015-07-03 18:28:22 -0600605 bios_cntl = ich_readb(priv, priv->bcr);
Jagan Teki69fd4c32015-10-23 01:37:56 +0530606 bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
Simon Glassba457562015-03-26 09:29:26 -0600607 bios_cntl |= 1; /* Write Protect Disable (WPD) */
Simon Glass50787922015-07-03 18:28:22 -0600608 ich_writeb(priv, bios_cntl, priv->bcr);
Simon Glassf2b85ab2016-01-18 20:19:21 -0700609 } else if (ret) {
610 debug("%s: Failed to disable write-protect: err=%d\n",
611 __func__, ret);
612 return ret;
Simon Glassba457562015-03-26 09:29:26 -0600613 }
614
615 priv->cur_speed = priv->max_speed;
616
617 return 0;
618}
619
Simon Glassba457562015-03-26 09:29:26 -0600620static int ich_spi_set_speed(struct udevice *bus, uint speed)
621{
622 struct ich_spi_priv *priv = dev_get_priv(bus);
623
624 priv->cur_speed = speed;
625
626 return 0;
627}
628
629static int ich_spi_set_mode(struct udevice *bus, uint mode)
630{
631 debug("%s: mode=%d\n", __func__, mode);
632
633 return 0;
634}
635
636static int ich_spi_child_pre_probe(struct udevice *dev)
637{
638 struct udevice *bus = dev_get_parent(dev);
639 struct ich_spi_platdata *plat = dev_get_platdata(bus);
640 struct ich_spi_priv *priv = dev_get_priv(bus);
Simon Glassbcbe3d12015-09-28 23:32:01 -0600641 struct spi_slave *slave = dev_get_parent_priv(dev);
Simon Glassba457562015-03-26 09:29:26 -0600642
643 /*
644 * Yes this controller can only write a small number of bytes at
645 * once! The limit is typically 64 bytes.
646 */
647 slave->max_write_size = priv->databytes;
648 /*
649 * ICH 7 SPI controller only supports array read command
650 * and byte program command for SST flash
651 */
Bin Meng6e670b52016-02-01 01:40:38 -0800652 if (plat->ich_version == ICHV_7) {
Jagan Teki91292e02015-12-16 15:24:24 +0530653 slave->mode_rx = SPI_RX_SLOW;
Jagan Tekicdf33932015-12-13 20:12:45 +0530654 slave->mode = SPI_TX_BYTE;
Simon Glassba457562015-03-26 09:29:26 -0600655 }
656
657 return 0;
658}
659
Bin Meng1f9eb592016-02-01 01:40:37 -0800660static int ich_spi_ofdata_to_platdata(struct udevice *dev)
661{
662 struct ich_spi_platdata *plat = dev_get_platdata(dev);
663 int ret;
664
665 ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
666 "intel,ich7-spi");
667 if (ret == 0) {
Bin Meng6e670b52016-02-01 01:40:38 -0800668 plat->ich_version = ICHV_7;
Bin Meng1f9eb592016-02-01 01:40:37 -0800669 } else {
670 ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
671 "intel,ich9-spi");
672 if (ret == 0)
Bin Meng6e670b52016-02-01 01:40:38 -0800673 plat->ich_version = ICHV_9;
Bin Meng1f9eb592016-02-01 01:40:37 -0800674 }
675
676 return ret;
677}
678
Simon Glassba457562015-03-26 09:29:26 -0600679static const struct dm_spi_ops ich_spi_ops = {
680 .xfer = ich_spi_xfer,
681 .set_speed = ich_spi_set_speed,
682 .set_mode = ich_spi_set_mode,
683 /*
684 * cs_info is not needed, since we require all chip selects to be
685 * in the device tree explicitly
686 */
687};
688
689static const struct udevice_id ich_spi_ids[] = {
Bin Meng1f9eb592016-02-01 01:40:37 -0800690 { .compatible = "intel,ich7-spi" },
691 { .compatible = "intel,ich9-spi" },
Simon Glassba457562015-03-26 09:29:26 -0600692 { }
693};
694
695U_BOOT_DRIVER(ich_spi) = {
696 .name = "ich_spi",
697 .id = UCLASS_SPI,
698 .of_match = ich_spi_ids,
699 .ops = &ich_spi_ops,
Bin Meng1f9eb592016-02-01 01:40:37 -0800700 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
Simon Glassba457562015-03-26 09:29:26 -0600701 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
702 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
703 .child_pre_probe = ich_spi_child_pre_probe,
704 .probe = ich_spi_probe,
705};