| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Thomas Abraham | e39448e | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Samsung Electronics |
| 4 | * Thomas Abraham <thomas.ab@samsung.com> |
| Thomas Abraham | e39448e | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <asm/armv8/mmu.h> |
| 9 | |
| Thomas Abraham | e39448e | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 10 | #ifdef CONFIG_EXYNOS7420 |
| 11 | static struct mm_region exynos7420_mem_map[] = { |
| 12 | { |
| York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 13 | .virt = 0x10000000UL, |
| 14 | .phys = 0x10000000UL, |
| Thomas Abraham | e39448e | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 15 | .size = 0x10000000UL, |
| 16 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 17 | PTE_BLOCK_NON_SHARE | |
| 18 | PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
| 19 | }, { |
| York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 20 | .virt = 0x40000000UL, |
| 21 | .phys = 0x40000000UL, |
| Thomas Abraham | e39448e | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 22 | .size = 0x80000000UL, |
| 23 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 24 | PTE_BLOCK_INNER_SHARE, |
| 25 | }, { |
| 26 | /* List terminator */ |
| Thomas Abraham | e39448e | 2016-04-23 22:18:13 +0530 | [diff] [blame] | 27 | }, |
| 28 | }; |
| 29 | |
| 30 | struct mm_region *mem_map = exynos7420_mem_map; |
| 31 | #endif |
| Dzmitry Sankouski | 69bde04 | 2021-10-17 13:45:41 +0300 | [diff] [blame^] | 32 | |
| 33 | #ifdef CONFIG_EXYNOS7870 |
| 34 | static struct mm_region exynos7870_mem_map[] = { |
| 35 | { |
| 36 | .virt = 0x10000000UL, |
| 37 | .phys = 0x10000000UL, |
| 38 | .size = 0x10000000UL, |
| 39 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 40 | PTE_BLOCK_NON_SHARE | |
| 41 | PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
| 42 | }, |
| 43 | { |
| 44 | .virt = 0x40000000UL, |
| 45 | .phys = 0x40000000UL, |
| 46 | .size = 0x3E400000UL, |
| 47 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 48 | PTE_BLOCK_INNER_SHARE, |
| 49 | }, |
| 50 | { |
| 51 | .virt = 0x80000000UL, |
| 52 | .phys = 0x80000000UL, |
| 53 | .size = 0x40000000UL, |
| 54 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 55 | PTE_BLOCK_INNER_SHARE, |
| 56 | }, |
| 57 | |
| 58 | { |
| 59 | /* List terminator */ |
| 60 | }, |
| 61 | }; |
| 62 | |
| 63 | struct mm_region *mem_map = exynos7870_mem_map; |
| 64 | #endif |
| 65 | |
| 66 | #ifdef CONFIG_EXYNOS7880 |
| 67 | static struct mm_region exynos7880_mem_map[] = { |
| 68 | { |
| 69 | .virt = 0x10000000UL, |
| 70 | .phys = 0x10000000UL, |
| 71 | .size = 0x10000000UL, |
| 72 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 73 | PTE_BLOCK_NON_SHARE | |
| 74 | PTE_BLOCK_PXN | PTE_BLOCK_UXN, |
| 75 | }, |
| 76 | { |
| 77 | .virt = 0x40000000UL, |
| 78 | .phys = 0x40000000UL, |
| 79 | .size = 0x3E400000UL, |
| 80 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 81 | PTE_BLOCK_INNER_SHARE, |
| 82 | }, |
| 83 | { |
| 84 | .virt = 0x80000000UL, |
| 85 | .phys = 0x80000000UL, |
| 86 | .size = 0x80000000UL, |
| 87 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 88 | PTE_BLOCK_INNER_SHARE, |
| 89 | }, |
| 90 | |
| 91 | { |
| 92 | /* List terminator */ |
| 93 | }, |
| 94 | }; |
| 95 | |
| 96 | struct mm_region *mem_map = exynos7880_mem_map; |
| 97 | #endif |