blob: 92b2179ca7f5ad8693dd1df24f3432c9e13c1a3d [file] [log] [blame]
York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * Corenet DS style board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_RAMBOOT_PBL
30#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
31#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Shaohui Xiec79fd502013-03-25 07:40:02 +000032#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg
33#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg
York Sunee52b182012-10-11 07:13:37 +000034#endif
35
Liu Gang69fdf902013-05-07 16:30:50 +080036#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
37/* Set 1M boot space */
38#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
39#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
40 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
41#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
42#define CONFIG_SYS_NO_FLASH
43#endif
44
York Sunee52b182012-10-11 07:13:37 +000045#define CONFIG_CMD_REGINFO
46
47/* High Level Configuration Options */
48#define CONFIG_BOOKE
York Sunee52b182012-10-11 07:13:37 +000049#define CONFIG_E500 /* BOOKE e500 family */
50#define CONFIG_E500MC /* BOOKE e500mc family */
51#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
52#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
53#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
54#define CONFIG_MP /* support multiple processors */
55
56#ifndef CONFIG_SYS_TEXT_BASE
57#define CONFIG_SYS_TEXT_BASE 0xeff80000
58#endif
59
60#ifndef CONFIG_RESET_VECTOR_ADDRESS
61#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62#endif
63
64#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
65#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
66#define CONFIG_FSL_IFC /* Enable IFC Support */
67#define CONFIG_PCI /* Enable PCI/PCIE */
68#define CONFIG_PCIE1 /* PCIE controler 1 */
69#define CONFIG_PCIE2 /* PCIE controler 2 */
70#define CONFIG_PCIE3 /* PCIE controler 3 */
71#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
72#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
73
74#define CONFIG_SYS_SRIO
75#define CONFIG_SRIO1 /* SRIO port 1 */
76#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gang3e531b02013-05-07 16:30:49 +080077#define CONFIG_SRIO_PCIE_BOOT_MASTER
York Sunee52b182012-10-11 07:13:37 +000078
79#define CONFIG_FSL_LAW /* Use common FSL init code */
80
81#define CONFIG_ENV_OVERWRITE
82
83#ifdef CONFIG_SYS_NO_FLASH
Liu Gang69fdf902013-05-07 16:30:50 +080084#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
York Sunee52b182012-10-11 07:13:37 +000085#define CONFIG_ENV_IS_NOWHERE
Liu Gang69fdf902013-05-07 16:30:50 +080086#endif
York Sunee52b182012-10-11 07:13:37 +000087#else
88#define CONFIG_FLASH_CFI_DRIVER
89#define CONFIG_SYS_FLASH_CFI
90#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
91#endif
92
York Sunee52b182012-10-11 07:13:37 +000093#if defined(CONFIG_SPIFLASH)
94#define CONFIG_SYS_EXTRA_ENV_RELOC
95#define CONFIG_ENV_IS_IN_SPI_FLASH
96#define CONFIG_ENV_SPI_BUS 0
97#define CONFIG_ENV_SPI_CS 0
98#define CONFIG_ENV_SPI_MAX_HZ 10000000
99#define CONFIG_ENV_SPI_MODE 0
100#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
101#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
102#define CONFIG_ENV_SECT_SIZE 0x10000
103#elif defined(CONFIG_SDCARD)
104#define CONFIG_SYS_EXTRA_ENV_RELOC
105#define CONFIG_ENV_IS_IN_MMC
106#define CONFIG_SYS_MMC_ENV_DEV 0
107#define CONFIG_ENV_SIZE 0x2000
108#define CONFIG_ENV_OFFSET (512 * 1097)
109#elif defined(CONFIG_NAND)
110#define CONFIG_SYS_EXTRA_ENV_RELOC
111#define CONFIG_ENV_IS_IN_NAND
112#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
113#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang69fdf902013-05-07 16:30:50 +0800114#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
115#define CONFIG_ENV_IS_IN_REMOTE
116#define CONFIG_ENV_ADDR 0xffe20000
117#define CONFIG_ENV_SIZE 0x2000
118#elif defined(CONFIG_ENV_IS_NOWHERE)
119#define CONFIG_ENV_SIZE 0x2000
York Sunee52b182012-10-11 07:13:37 +0000120#else
121#define CONFIG_ENV_IS_IN_FLASH
122#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
123#define CONFIG_ENV_SIZE 0x2000
124#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
125#endif
York Sunee52b182012-10-11 07:13:37 +0000126
127#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
128#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
129
130#ifndef __ASSEMBLY__
131unsigned long get_board_sys_clk(void);
132unsigned long get_board_ddr_clk(void);
133#endif
134
135/*
136 * These can be toggled for performance analysis, otherwise use default.
137 */
138#define CONFIG_SYS_CACHE_STASHING
139#define CONFIG_BTB /* toggle branch predition */
140#define CONFIG_DDR_ECC
141#ifdef CONFIG_DDR_ECC
142#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
143#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
144#endif
145
146#define CONFIG_ENABLE_36BIT_PHYS
147
148#ifdef CONFIG_PHYS_64BIT
149#define CONFIG_ADDR_MAP
150#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
151#endif
152
153#if 0
154#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
155#endif
156#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
157#define CONFIG_SYS_MEMTEST_END 0x00400000
158#define CONFIG_SYS_ALT_MEMTEST
159#define CONFIG_PANIC_HANG /* do not reset board on panic */
160
161/*
162 * Config the L3 Cache as L3 SRAM
163 */
164#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
165
166#ifdef CONFIG_PHYS_64BIT
167#define CONFIG_SYS_DCSRBAR 0xf0000000
168#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
169#endif
170
171/* EEPROM */
172#define CONFIG_ID_EEPROM
173#define CONFIG_SYS_I2C_EEPROM_NXID
174#define CONFIG_SYS_EEPROM_BUS_NUM 0
175#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
176#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
177
178/*
179 * DDR Setup
180 */
181#define CONFIG_VERY_BIG_RAM
182#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
183#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
184
185/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
186#define CONFIG_DIMM_SLOTS_PER_CTLR 2
187#define CONFIG_CHIP_SELECTS_PER_CTRL 4
188#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
189
190#define CONFIG_DDR_SPD
191#define CONFIG_FSL_DDR3
192
193#define CONFIG_SYS_SPD_BUS_NUM 0
194#define SPD_EEPROM_ADDRESS1 0x51
195#define SPD_EEPROM_ADDRESS2 0x52
196#define SPD_EEPROM_ADDRESS3 0x53
197#define SPD_EEPROM_ADDRESS4 0x54
198#define SPD_EEPROM_ADDRESS5 0x55
199#define SPD_EEPROM_ADDRESS6 0x56
200#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
201#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
202
203/*
204 * IFC Definitions
205 */
206#define CONFIG_SYS_FLASH_BASE 0xe0000000
207#ifdef CONFIG_PHYS_64BIT
208#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
209#else
210#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
211#endif
212
213#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
214#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
215 + 0x8000000) | \
216 CSPR_PORT_SIZE_16 | \
217 CSPR_MSEL_NOR | \
218 CSPR_V)
219#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
220#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
221 CSPR_PORT_SIZE_16 | \
222 CSPR_MSEL_NOR | \
223 CSPR_V)
224#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
225/* NOR Flash Timing Params */
226#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
227
York Sun9730b7b2012-12-19 17:23:05 +0000228#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
229 FTIM0_NOR_TEADC(0x5) | \
230 FTIM0_NOR_TEAHC(0x5))
York Sunee52b182012-10-11 07:13:37 +0000231#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
232 FTIM1_NOR_TRAD_NOR(0x1A) |\
233 FTIM1_NOR_TSEQRAD_NOR(0x13))
York Sun9730b7b2012-12-19 17:23:05 +0000234#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
235 FTIM2_NOR_TCH(0x4) | \
York Sunee52b182012-10-11 07:13:37 +0000236 FTIM2_NOR_TWPH(0x0E) | \
237 FTIM2_NOR_TWP(0x1c))
238#define CONFIG_SYS_NOR_FTIM3 0x0
239
240#define CONFIG_SYS_FLASH_QUIET_TEST
241#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
242
243#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
244#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
245#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
246#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
247
248#define CONFIG_SYS_FLASH_EMPTY_INFO
249#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
250 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
251
252#define CONFIG_FSL_QIXIS /* use common QIXIS code */
253#define QIXIS_BASE 0xffdf0000
254#define QIXIS_LBMAP_SWITCH 6
255#define QIXIS_LBMAP_MASK 0x0f
256#define QIXIS_LBMAP_SHIFT 0
257#define QIXIS_LBMAP_DFLTBANK 0x00
258#define QIXIS_LBMAP_ALTBANK 0x04
259#define QIXIS_RST_CTL_RESET 0x83
260#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
261#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
262#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
263#ifdef CONFIG_PHYS_64BIT
264#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
265#else
266#define QIXIS_BASE_PHYS QIXIS_BASE
267#endif
268
269#define CONFIG_SYS_CSPR3_EXT (0xf)
270#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
271 | CSPR_PORT_SIZE_8 \
272 | CSPR_MSEL_GPCM \
273 | CSPR_V)
Prabhakar Kushwaha9427ba52012-12-18 17:23:19 +0000274#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
York Sunee52b182012-10-11 07:13:37 +0000275#define CONFIG_SYS_CSOR3 0x0
276/* QIXIS Timing parameters for IFC CS3 */
277#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
278 FTIM0_GPCM_TEADC(0x0e) | \
279 FTIM0_GPCM_TEAHC(0x0e))
280#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
281 FTIM1_GPCM_TRAD(0x3f))
282#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
283 FTIM2_GPCM_TCH(0x0) | \
284 FTIM2_GPCM_TWP(0x1f))
285#define CONFIG_SYS_CS3_FTIM3 0x0
286
287/* NAND Flash on IFC */
288#define CONFIG_NAND_FSL_IFC
289#define CONFIG_SYS_NAND_BASE 0xff800000
290#ifdef CONFIG_PHYS_64BIT
291#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
292#else
293#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
294#endif
295
296#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
297#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
298 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
299 | CSPR_MSEL_NAND /* MSEL = NAND */ \
300 | CSPR_V)
301#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
302
303#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
304 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
305 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
306 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
307 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
308 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
309 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
310
311#define CONFIG_SYS_NAND_ONFI_DETECTION
312
313/* ONFI NAND Flash mode0 Timing Params */
314#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
315 FTIM0_NAND_TWP(0x18) | \
316 FTIM0_NAND_TWCHT(0x07) | \
317 FTIM0_NAND_TWH(0x0a))
318#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
319 FTIM1_NAND_TWBE(0x39) | \
320 FTIM1_NAND_TRR(0x0e) | \
321 FTIM1_NAND_TRP(0x18))
322#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
323 FTIM2_NAND_TREH(0x0a) | \
324 FTIM2_NAND_TWHRE(0x1e))
325#define CONFIG_SYS_NAND_FTIM3 0x0
326
327#define CONFIG_SYS_NAND_DDR_LAW 11
328
329#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
330#define CONFIG_SYS_MAX_NAND_DEVICE 1
331#define CONFIG_MTD_NAND_VERIFY_WRITE
332#define CONFIG_CMD_NAND
333
334#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
335
336#if defined(CONFIG_NAND)
337#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
338#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
339#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
340#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
341#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
342#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
343#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
344#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
345#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
346#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
347#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
348#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
349#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
350#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
351#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
352#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
353#else
354#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
355#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
356#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
357#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
358#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
359#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
360#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
361#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
362#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
363#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
364#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
365#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
366#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
367#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
368#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
369#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
370#endif
371#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
372#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
373#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
374#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
375#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
376#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
377#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
378#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
379
380#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
381
382#if defined(CONFIG_RAMBOOT_PBL)
383#define CONFIG_SYS_RAMBOOT
384#endif
385
386#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
387#define CONFIG_MISC_INIT_R
388
389#define CONFIG_HWCONFIG
390
391/* define to use L1 as initial stack */
392#define CONFIG_L1_INIT_RAM
393#define CONFIG_SYS_INIT_RAM_LOCK
394#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
395#ifdef CONFIG_PHYS_64BIT
396#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
397#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
398/* The assembler doesn't like typecast */
399#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
400 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
401 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
402#else
403#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
404#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
405#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
406#endif
407#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
408
409#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
410 GENERATED_GBL_DATA_SIZE)
411#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
412
413#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
414#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
415
416/* Serial Port - controlled on board with jumper J8
417 * open - index 2
418 * shorted - index 1
419 */
420#define CONFIG_CONS_INDEX 1
421#define CONFIG_SYS_NS16550
422#define CONFIG_SYS_NS16550_SERIAL
423#define CONFIG_SYS_NS16550_REG_SIZE 1
424#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
425
426#define CONFIG_SYS_BAUDRATE_TABLE \
427 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
428
429#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
430#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
431#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
432#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
433
434/* Use the HUSH parser */
435#define CONFIG_SYS_HUSH_PARSER
436#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
437
438/* pass open firmware flat tree */
439#define CONFIG_OF_LIBFDT
440#define CONFIG_OF_BOARD_SETUP
441#define CONFIG_OF_STDOUT_VIA_ALIAS
442
443/* new uImage format support */
444#define CONFIG_FIT
445#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
446
447/* I2C */
448#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
449#define CONFIG_HARD_I2C /* I2C with hardware support */
450#define CONFIG_I2C_MULTI_BUS
451#define CONFIG_I2C_CMD_TREE
452#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
453#define CONFIG_SYS_I2C_SLAVE 0x7F
454#define CONFIG_SYS_I2C_OFFSET 0x118000
455#define CONFIG_SYS_I2C2_OFFSET 0x118100
456#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
457#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
458
York Sunee52b182012-10-11 07:13:37 +0000459#define I2C_MUX_CH_DEFAULT 0x8
York Sun97c7fe62013-03-25 07:33:22 +0000460#define I2C_MUX_CH_VOL_MONITOR 0xa
York Sunee52b182012-10-11 07:13:37 +0000461#define I2C_MUX_CH_VSC3316_FS 0xc
462#define I2C_MUX_CH_VSC3316_BS 0xd
York Sun97c7fe62013-03-25 07:33:22 +0000463
464/* Voltage monitor on channel 2*/
465#define I2C_VOL_MONITOR_ADDR 0x40
466#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
467#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
468#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
469
470/* VSC Crossbar switches */
471#define CONFIG_VSC_CROSSBAR
York Sunee52b182012-10-11 07:13:37 +0000472#define VSC3316_FSM_TX_ADDR 0x70
473#define VSC3316_FSM_RX_ADDR 0x71
474
475/*
476 * RapidIO
477 */
478#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
479#ifdef CONFIG_PHYS_64BIT
480#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
481#else
482#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
483#endif
484#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
485
486#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
487#ifdef CONFIG_PHYS_64BIT
488#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
489#else
490#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
491#endif
492#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
493
494/*
495 * for slave u-boot IMAGE instored in master memory space,
496 * PHYS must be aligned based on the SIZE
497 */
498#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
499#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
500#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
501#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
502/*
503 * for slave UCODE and ENV instored in master memory space,
504 * PHYS must be aligned based on the SIZE
505 */
506#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
507#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
508#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
509
510/* slave core release by master*/
511#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
512#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
513
514/*
515 * SRIO_PCIE_BOOT - SLAVE
516 */
517#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
518#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
519#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
520 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
521#endif
522/*
523 * eSPI - Enhanced SPI
524 */
525#define CONFIG_FSL_ESPI
526#define CONFIG_SPI_FLASH
Shaohui Xie7ff8c7c2013-03-25 07:33:13 +0000527#define CONFIG_SPI_FLASH_SST
York Sunee52b182012-10-11 07:13:37 +0000528#define CONFIG_CMD_SF
529#define CONFIG_SF_DEFAULT_SPEED 10000000
530#define CONFIG_SF_DEFAULT_MODE 0
531
532/*
533 * General PCI
534 * Memory space is mapped 1-1, but I/O space must start from 0.
535 */
536
537/* controller 1, direct to uli, tgtid 3, Base address 20000 */
538#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
539#ifdef CONFIG_PHYS_64BIT
540#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
541#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
542#else
543#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
544#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
545#endif
546#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
547#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
548#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
549#ifdef CONFIG_PHYS_64BIT
550#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
551#else
552#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
553#endif
554#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
555
556/* controller 2, Slot 2, tgtid 2, Base address 201000 */
557#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
558#ifdef CONFIG_PHYS_64BIT
559#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
560#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
561#else
562#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
563#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
564#endif
565#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
566#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
567#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
568#ifdef CONFIG_PHYS_64BIT
569#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
570#else
571#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
572#endif
573#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
574
575/* controller 3, Slot 1, tgtid 1, Base address 202000 */
576#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
577#ifdef CONFIG_PHYS_64BIT
578#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
579#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
580#else
581#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
582#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
583#endif
584#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
585#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
586#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
587#ifdef CONFIG_PHYS_64BIT
588#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
589#else
590#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
591#endif
592#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
593
594/* controller 4, Base address 203000 */
595#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
596#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
597#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
598#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
599#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
600#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
601
602/* Qman/Bman */
603#ifndef CONFIG_NOBQFMAN
604#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
605#define CONFIG_SYS_BMAN_NUM_PORTALS 50
606#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
607#ifdef CONFIG_PHYS_64BIT
608#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
609#else
610#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
611#endif
612#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
613#define CONFIG_SYS_QMAN_NUM_PORTALS 50
614#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
615#ifdef CONFIG_PHYS_64BIT
616#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
617#else
618#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
619#endif
620#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
621
622#define CONFIG_SYS_DPAA_FMAN
623#define CONFIG_SYS_DPAA_PME
624#define CONFIG_SYS_PMAN
625#define CONFIG_SYS_DPAA_DCE
626#define CONFIG_SYS_INTERLAKEN
627
628/* Default address of microcode for the Linux Fman driver */
629#if defined(CONFIG_SPIFLASH)
630/*
631 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
632 * env, so we got 0x110000.
633 */
634#define CONFIG_SYS_QE_FW_IN_SPIFLASH
635#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
636#elif defined(CONFIG_SDCARD)
637/*
638 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
639 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
640 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
641 */
642#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
643#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
644#elif defined(CONFIG_NAND)
645#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
646#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang69fdf902013-05-07 16:30:50 +0800647#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
648/*
649 * Slave has no ucode locally, it can fetch this from remote. When implementing
650 * in two corenet boards, slave's ucode could be stored in master's memory
651 * space, the address can be mapped from slave TLB->slave LAW->
652 * slave SRIO or PCIE outbound window->master inbound window->
653 * master LAW->the ucode address in master's memory space.
654 */
655#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
656#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
York Sunee52b182012-10-11 07:13:37 +0000657#else
658#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
659#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
660#endif
661#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
662#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
663#endif /* CONFIG_NOBQFMAN */
664
665#ifdef CONFIG_SYS_DPAA_FMAN
666#define CONFIG_FMAN_ENET
667#define CONFIG_PHYLIB_10G
668#define CONFIG_PHY_VITESSE
669#define CONFIG_PHY_TERANETICS
670#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
671#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
672#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
673#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
Shaohui Xie4e5c9262013-03-25 07:33:16 +0000674#define FM1_10GEC1_PHY_ADDR 0x0
675#define FM1_10GEC2_PHY_ADDR 0x1
676#define FM2_10GEC1_PHY_ADDR 0x2
677#define FM2_10GEC2_PHY_ADDR 0x3
York Sunee52b182012-10-11 07:13:37 +0000678#endif
679
680#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000681#define CONFIG_PCI_INDIRECT_BRIDGE
York Sunee52b182012-10-11 07:13:37 +0000682#define CONFIG_NET_MULTI
683#define CONFIG_PCI_PNP /* do pci plug-and-play */
684#define CONFIG_E1000
685
686#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
687#define CONFIG_DOS_PARTITION
688#endif /* CONFIG_PCI */
689
690/* SATA */
691#ifdef CONFIG_FSL_SATA_V2
692#define CONFIG_LIBATA
693#define CONFIG_FSL_SATA
694
695#define CONFIG_SYS_SATA_MAX_DEVICE 2
696#define CONFIG_SATA1
697#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
698#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
699#define CONFIG_SATA2
700#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
701#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
702
703#define CONFIG_LBA48
704#define CONFIG_CMD_SATA
705#define CONFIG_DOS_PARTITION
706#define CONFIG_CMD_EXT2
707#endif
708
709#ifdef CONFIG_FMAN_ENET
710#define CONFIG_MII /* MII PHY management */
711#define CONFIG_ETHPRIME "FM1@DTSEC1"
712#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
713#endif
714
715/*
716 * Environment
717 */
718#define CONFIG_LOADS_ECHO /* echo on for serial download */
719#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
720
721/*
722 * Command line configuration.
723 */
724#include <config_cmd_default.h>
725
726#define CONFIG_CMD_DHCP
727#define CONFIG_CMD_ELF
728#define CONFIG_CMD_ERRATA
729#define CONFIG_CMD_GREPENV
730#define CONFIG_CMD_IRQ
731#define CONFIG_CMD_I2C
732#define CONFIG_CMD_MII
733#define CONFIG_CMD_PING
734#define CONFIG_CMD_SETEXPR
735
736#ifdef CONFIG_PCI
737#define CONFIG_CMD_PCI
738#define CONFIG_CMD_NET
739#endif
740
741/*
742* USB
743*/
744#define CONFIG_CMD_USB
745#define CONFIG_USB_STORAGE
746#define CONFIG_USB_EHCI
747#define CONFIG_USB_EHCI_FSL
748#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
749#define CONFIG_CMD_EXT2
750#define CONFIG_HAS_FSL_DR_USB
751
752#define CONFIG_MMC
753
754#ifdef CONFIG_MMC
755#define CONFIG_FSL_ESDHC
756#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
757#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
758#define CONFIG_CMD_MMC
759#define CONFIG_GENERIC_MMC
760#define CONFIG_CMD_EXT2
761#define CONFIG_CMD_FAT
762#define CONFIG_DOS_PARTITION
763#endif
764
765/*
766 * Miscellaneous configurable options
767 */
768#define CONFIG_SYS_LONGHELP /* undef to save memory */
769#define CONFIG_CMDLINE_EDITING /* Command-line editing */
770#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
771#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
772#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
773#ifdef CONFIG_CMD_KGDB
774#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
775#else
776#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
777#endif
778#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
779#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
780#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
781#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
782
783/*
784 * For booting Linux, the board info and command line data
785 * have to be in the first 64 MB of memory, since this is
786 * the maximum mapped by the Linux kernel during initialization.
787 */
788#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
789#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
790
791#ifdef CONFIG_CMD_KGDB
792#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
793#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
794#endif
795
796/*
797 * Environment Configuration
798 */
799#define CONFIG_ROOTPATH "/opt/nfsroot"
800#define CONFIG_BOOTFILE "uImage"
801#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
802
803/* default location for tftp and bootm */
804#define CONFIG_LOADADDR 1000000
805
806#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
807
808#define CONFIG_BAUDRATE 115200
809
810#define __USB_PHY_TYPE utmi
811
York Sun10d644b2013-03-25 07:33:31 +0000812/*
813 * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be
814 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to
815 * cacheline interleaving. It can be cacheline, page, bank, superbank.
816 * See doc/README.fsl-ddr for details.
817 */
818#ifdef CONFIG_PPC_T4240
819#define CTRL_INTLV_PREFERED 3way_4KB
820#else
821#define CTRL_INTLV_PREFERED cacheline
822#endif
823
York Sunee52b182012-10-11 07:13:37 +0000824#define CONFIG_EXTRA_ENV_SETTINGS \
York Sun10d644b2013-03-25 07:33:31 +0000825 "hwconfig=fsl_ddr:" \
826 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
York Sunee52b182012-10-11 07:13:37 +0000827 "bank_intlv=auto;" \
828 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
829 "netdev=eth0\0" \
830 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
831 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
832 "tftpflash=tftpboot $loadaddr $uboot && " \
833 "protect off $ubootaddr +$filesize && " \
834 "erase $ubootaddr +$filesize && " \
835 "cp.b $loadaddr $ubootaddr $filesize && " \
836 "protect on $ubootaddr +$filesize && " \
837 "cmp.b $loadaddr $ubootaddr $filesize\0" \
838 "consoledev=ttyS0\0" \
839 "ramdiskaddr=2000000\0" \
840 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
841 "fdtaddr=c00000\0" \
842 "fdtfile=t4240qds/t4240qds.dtb\0" \
843 "bdev=sda3\0" \
844 "c=ffe\0"
845
846/* For emulation this causes u-boot to jump to the start of the proof point
847 app code automatically */
848#define CONFIG_PROOF_POINTS \
849 "setenv bootargs root=/dev/$bdev rw " \
850 "console=$consoledev,$baudrate $othbootargs;" \
851 "cpu 1 release 0x29000000 - - -;" \
852 "cpu 2 release 0x29000000 - - -;" \
853 "cpu 3 release 0x29000000 - - -;" \
854 "cpu 4 release 0x29000000 - - -;" \
855 "cpu 5 release 0x29000000 - - -;" \
856 "cpu 6 release 0x29000000 - - -;" \
857 "cpu 7 release 0x29000000 - - -;" \
858 "go 0x29000000"
859
860#define CONFIG_HVBOOT \
861 "setenv bootargs config-addr=0x60000000; " \
862 "bootm 0x01000000 - 0x00f00000"
863
864#define CONFIG_ALU \
865 "setenv bootargs root=/dev/$bdev rw " \
866 "console=$consoledev,$baudrate $othbootargs;" \
867 "cpu 1 release 0x01000000 - - -;" \
868 "cpu 2 release 0x01000000 - - -;" \
869 "cpu 3 release 0x01000000 - - -;" \
870 "cpu 4 release 0x01000000 - - -;" \
871 "cpu 5 release 0x01000000 - - -;" \
872 "cpu 6 release 0x01000000 - - -;" \
873 "cpu 7 release 0x01000000 - - -;" \
874 "go 0x01000000"
875
876#define CONFIG_LINUX \
877 "setenv bootargs root=/dev/ram rw " \
878 "console=$consoledev,$baudrate $othbootargs;" \
879 "setenv ramdiskaddr 0x02000000;" \
880 "setenv fdtaddr 0x00c00000;" \
881 "setenv loadaddr 0x1000000;" \
882 "bootm $loadaddr $ramdiskaddr $fdtaddr"
883
884#define CONFIG_HDBOOT \
885 "setenv bootargs root=/dev/$bdev rw " \
886 "console=$consoledev,$baudrate $othbootargs;" \
887 "tftp $loadaddr $bootfile;" \
888 "tftp $fdtaddr $fdtfile;" \
889 "bootm $loadaddr - $fdtaddr"
890
891#define CONFIG_NFSBOOTCOMMAND \
892 "setenv bootargs root=/dev/nfs rw " \
893 "nfsroot=$serverip:$rootpath " \
894 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
895 "console=$consoledev,$baudrate $othbootargs;" \
896 "tftp $loadaddr $bootfile;" \
897 "tftp $fdtaddr $fdtfile;" \
898 "bootm $loadaddr - $fdtaddr"
899
900#define CONFIG_RAMBOOTCOMMAND \
901 "setenv bootargs root=/dev/ram rw " \
902 "console=$consoledev,$baudrate $othbootargs;" \
903 "tftp $ramdiskaddr $ramdiskfile;" \
904 "tftp $loadaddr $bootfile;" \
905 "tftp $fdtaddr $fdtfile;" \
906 "bootm $loadaddr $ramdiskaddr $fdtaddr"
907
908#define CONFIG_BOOTCOMMAND CONFIG_LINUX
909
910#ifdef CONFIG_SECURE_BOOT
911#include <asm/fsl_secure_boot.h>
912#endif
913
914#endif /* __CONFIG_H */